公开(公告)号：US09947673B1

公开(公告)日：2018-04-17

申请号：US15479253

申请日：2017-04-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Chia Chang ,  Shih-Hao Liang ,  Chun-Yen Tseng ,  Yu-Tse Kuo ,  Ching-Cheng Lung ,  Hung-Chan Lin ,  Shao-Hui Wu

IPC: H01L27/02 ,  H01L27/11 ,  G11C11/412 ,  H01L29/24

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C14/0054 ,  H01L27/0207 ,  H01L27/1116 ,  H01L29/24

Abstract: The present invention provides a semiconductor memory device, includes at least one static random access memory (SRAM) cell, wherein the SRAM cell includes a first pick-up node, and a dielectric oxide SRAM (DOSRAM), disposed in a first dielectric layer and disposed above the SRAM cell when viewed in a cross section view, wherein the DOSRAM includes an oxide semiconductor filed effect transistor (OSFET) and a capacitor, a source of the OSFET is electrically connected to the first pick-up node of the SRAM cell through a via structure, and at least parts of the first dielectric layer are disposed between the source of the OSFET and the via structure, and the capacitor is disposed above the OSFET and electrically connected to a drain of the OSFET when viewed in the cross section view.

公开(公告)号：US09851780B2

公开(公告)日：2017-12-26

申请号：US14829644

申请日：2015-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: G06F1/32 ,  G06F3/06 ,  H01L27/10 ,  H01L27/06 ,  H01L27/07 ,  H01L27/108 ,  G11C16/00 ,  G11C7/10 ,  G11C5/14

CPC classification number: G06F1/3293 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G11C5/141 ,  G11C7/1006 ,  G11C16/00 ,  G11C2211/4016 ,  H01L27/06 ,  H01L27/07 ,  H01L27/108

Abstract: A semiconductor device includes a main processor, a normally-off processor, and at least one oxide semiconductor random access memory (RAM). The normally-off processor includes at least one oxide semiconductor transistor. The main processor is connected to the normally-off processor, and a clock rate of the main processor is higher than a clock rate of the normally-off processor. The oxide semiconductor RAM is connected to the normally-off processor. An operating method of the semiconductor includes backing up data from the main processor to the normally-off processor and/or the oxide semiconductor RAM.

公开(公告)号：US20170170256A1

公开(公告)日：2017-06-15

申请号：US14996244

申请日：2016-01-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L49/02

CPC classification number: H01L28/91

Abstract: A method for fabricating capacitor is disclosed. The method includes the steps of: providing a material layer; forming a first conductive layer, a first dielectric layer, and a second conductive layer on the material layer; patterning the first dielectric layer and the second conductive layer to form a patterned first dielectric layer and a middle electrode; forming a second dielectric layer on the first conductive layer and the middle electrode; removing part of the second dielectric layer to form a patterned second dielectric layer; forming a third conductive layer on the first conductive layer and the patterned second dielectric layer, wherein the third conductive layer contacts the first conductive layer directly; and removing part of the third conductive layer to expose part of the patterned second dielectric layer.

公开(公告)号：US09620649B1

公开(公告)日：2017-04-11

申请号：US14960041

申请日：2015-12-04

Applicant: United Microelectronics Corp.

Inventor： Hai-Biao Yao ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Zhi-Biao Zhou

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L29/51

CPC classification number: H01L29/7869 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02565 ,  H01L21/0332 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/66969 ,  H01L29/785 ,  H01L29/78606 ,  H01L29/78696

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes an oxide semiconductor protrusion, a source, a drain, an oxide semiconductor layer, a first O-barrier layer, a gate electrode, a second O-barrier layer, and an H-barrier layer. The oxide semiconductor protrusion is disposed on an oxide substrate. The source and the drain are respectively disposed on opposite ends of the oxide semiconductor protrusion. The oxide semiconductor layer is disposed on the oxide substrate and covers the oxide semiconductor protrusion, the source, and the drain. The first O-barrier layer is disposed on the oxide semiconductor layer. The gate electrode is disposed on the first O-barrier layer and across the oxide semiconductor protrusion. The second O-barrier layer is disposed on the gate electrode. The H-barrier layer is disposed on the oxide substrate and covers the second O-barrier layer.

公开(公告)号：US20150357397A1

公开(公告)日：2015-12-10

申请号：US14445416

申请日：2014-07-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L28/60

Abstract: A semiconductor apparatus including a stacked capacitance structure is provided. The stacked capacitance structure includes a first inner metal layer having a first pad area adjacent to an edge of the first inner metal layer, a first insulating layer disposed on the first inner metal layer and exposing the first pad area, a second inner metal layer disposed on the first insulating layer and having a second pad area adjacent to an edge of the second inner metal layer, a second insulating layer disposed on the second inner metal layer and exposing the second pad area, and a third inner metal layer covering the second inner metal layer and including at least one first slit. The first pad area and the second pad area include a plurality of pads. The first slit corresponds to the second pad area, such that the pads on the second pad area are exposed.

Abstract translation: 提供了包括堆叠电容结构的半导体装置。 堆叠的电容结构包括具有与第一内金属层的边缘相邻的第一焊盘区域的第一内部金属层，设置在第一内部金属层上并暴露第一焊盘区域的第一绝缘层，设置的第二内部金属层 在第一绝缘层上并且具有与第二内金属层的边缘相邻的第二焊盘区域，设置在第二内金属层上并暴露第二焊盘区域的第二绝缘层，以及覆盖第二内金属层的第三内金属层 金属层并且包括至少一个第一狭缝。 第一焊盘区域和第二焊盘区域包括多个焊盘。 第一狭缝对应于第二焊盘区域，使得第二焊盘区域上的焊盘露出。

公开(公告)号：US10403743B2

公开(公告)日：2019-09-03

申请号：US15655881

申请日：2017-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xiang Li ,  Shao-Hui Wu ,  Hsiao Yu Chia ,  Yu-Cheng Tung

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/465

Abstract: A manufacturing method of an oxide semiconductor device includes the following steps. A first oxide semiconductor layer is formed on a substrate. A gate insulation layer is formed on the first oxide semiconductor layer. A first flattening process is performed on a top surface of the first oxide semiconductor layer before the step of forming the gate insulation layer. A roughness of the top surface of the first oxide semiconductor layer after the first flattening process is smaller than the roughness of the top surface of the first oxide semiconductor layer before the first flattening process.

公开(公告)号：US10115786B2

公开(公告)日：2018-10-30

申请号：US15352551

申请日：2016-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L49/02 ,  H01G11/24

Abstract: A capacitor includes: a bottom electrode; a middle electrode on the bottom electrode; a top electrode on the middle electrode; a first dielectric layer between the bottom electrode and the middle electrode; and a second dielectric layer between the middle electrode and the top electrode. Preferably, the second dielectric layer is disposed on at least a sidewall of the middle electrode to physically contact the first dielectrically, and the middle electrode includes a H-shape.

公开(公告)号：US20170179295A1

公开(公告)日：2017-06-22

申请号：US15447081

申请日：2017-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/04 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78603

Abstract: A semiconductor structure includes a substrate and a first element disposed in the substrate and arranged along a first direction. The first element is made of a semiconductor oxide material. The semiconductor structure also includes a dielectric layer disposed on the first element, and a second element, disposed on the dielectric layer and arranged along the first direction. The second element is used as a gate of a transistor structure.

公开(公告)号：US20170098712A1

公开(公告)日：2017-04-06

申请号：US14874546

申请日：2015-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Su Xing ,  Tien-Yu Hsieh

IPC: H01L29/786 ,  H01L27/108 ,  H01L27/115 ,  H01L29/66 ,  H01L49/02

CPC classification number: H01L27/1052 ,  H01L27/108 ,  H01L27/115 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/66742 ,  H01L29/7869

Abstract: A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection.

公开(公告)号：US20170084614A1

公开(公告)日：2017-03-23

申请号：US14856565

申请日：2015-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shao-Hui Wu ,  ZHIBIAO ZHOU ,  HAI BIAO YAO ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L27/108 ,  H01L29/786

CPC classification number: H01L27/10832 ,  H01L27/10867 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/7869

Abstract: A memory cell includes a substrate, a deep trench (DT) capacitor formed in the substrate, at least an insulting layer formed on the substrate, and an oxide semiconductor field effect transistor (OS FET) device formed on the insulating layer. And more important, the OS FET device is electrically connected to the DT capacitor.