公开(公告)号：US10177245B2

公开(公告)日：2019-01-08

申请号：US15660919

申请日：2017-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Shui-Yen Lu

IPC: H01L29/66 ,  H01L21/02

Abstract: A method of fabricating a semiconductor device is disclosed. A substrate is provided. A dummy gate stack is formed on the substrate. The dummy gate stack includes a gate dielectric layer and an amorphous silicon dummy gate on the gate dielectric layer. The amorphous silicon dummy gate is transformed into a nano-crystalline silicon dummy gate. A spacer is formed on a sidewall of the nano-crystalline silicon dummy gate. A source/drain region is formed in the substrate on either side of the dummy gate stack.

公开(公告)号：US10170624B2

公开(公告)日：2019-01-01

申请号：US15447134

申请日：2017-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhen-Cyuan Li ,  Nan-Yuan Huang ,  Shui-Yen Lu

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

Abstract: A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a first spacer structure and a source/drain region. The fin structure is disposed on the substrate, the gate structure is disposed on the fin structure. The fin structure includes an upper portion, a concave portion and a lower portion, and the concave portion is disposed between the upper portion and the lower portion. The first spacer structure is disposed on a sidewall of the gate structure. The first spacer structure includes a first spacer and a second spacer, wherein the first spacer is disposed between the second spacer, and a height of the first spacer is different from a height of the second spacer. The source/drain region is disposed in a semiconductor layer at two sides of the first spacer structure.

公开(公告)号：US10128366B2

公开(公告)日：2018-11-13

申请号：US15890303

申请日：2018-02-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Kuan Hsuan Ku ,  I-Cheng Hu ,  Chueh-Yang Liu ,  Shui-Yen Lu ,  Yu Shu Lin ,  Chun Yao Yang ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: H01L21/00 ,  H01L29/78 ,  H01L21/225 ,  H01L29/06 ,  H01L21/768 ,  H01L21/311 ,  H01L29/417 ,  H01L29/165 ,  H01L27/092

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.

公开(公告)号：US20180158943A1

公开(公告)日：2018-06-07

申请号：US15890303

申请日：2018-02-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Kuan Hsuan KU ,  I-Cheng Hu ,  Chueh-Yang Liu ,  Shui-Yen Lu ,  Yu Shu LIN ,  Chun Yao YANG ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/165 ,  H01L29/06 ,  H01L21/225 ,  H01L21/768 ,  H01L21/311 ,  H01L27/092

CPC classification number: H01L29/78 ,  H01L21/31144 ,  H01L21/76877 ,  H01L27/0922 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.

公开(公告)号：US20170338327A1

公开(公告)日：2017-11-23

申请号：US15186523

申请日：2016-06-19

Applicant: United Semiconductor (Xiamen) Co., Ltd. ,  UNITED MICROELECTRONICS CORP.

Inventor： Sheng-Hsu Liu ,  Jhen-Cyuan Li ,  Shui-Yen Lu

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/06 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/66553 ,  H01L21/30604 ,  H01L21/3085 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and a manufacturing method thereof, the semiconductor device includes two gate structures and an epitaxial structure. The two gate structures are disposed on a substrate. The epitaxial structure is disposed in the substrate between the gate structures, wherein a protruding portion of the substrate extends into the epitaxial structure in a protection direction.

公开(公告)号：US09755057B1

公开(公告)日：2017-09-05

申请号：US15221611

申请日：2016-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Shui-Yen Lu

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device is disclosed. A substrate is provided. A dummy gate stack is formed on the substrate. The dummy gate stack includes a gate dielectric layer and an amorphous silicon dummy gate on the gate dielectric layer. The amorphous silicon dummy gate is transformed into a nano-crystalline silicon dummy gate. A spacer is formed on a sidewall of the nano-crystalline silicon dummy gate. A source/drain region is formed in the substrate on either side of the dummy gate stack.

公开(公告)号：US09614034B1

公开(公告)日：2017-04-04

申请号：US14884787

申请日：2015-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhen-Cyuan Li ,  Nan-Yuan Huang ,  Shui-Yen Lu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L21/76232 ,  H01L29/66795 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate, having a recess disposed therein, an insulating layer filled in the recess and disposed on a surface of the substrate, and at least one fin structure disposed in the insulating layer, the fin structure consisting of two terminal parts and a central part disposed between two terminal parts. The terminal parts are disposed on the surface of the substrate and directly contact the substrate, and the central part is disposed right above the recess.

公开(公告)号：US20170005015A1

公开(公告)日：2017-01-05

申请号：US14791241

申请日：2015-07-02

Applicant: United Microelectronics Corp.

Inventor： Jhen-Cyuan Li ,  Yi-Lin Chen ,  Shui-Yen Lu

IPC: H01L21/66 ,  H01L21/027 ,  H01L21/306 ,  H01L23/544 ,  H01L21/8238

CPC classification number: H01L22/12 ,  G03F7/70633 ,  H01L21/0274 ,  H01L21/8238 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A monitor process for lithography and etching processes includes the following steps. A first lithography process and a first etching process are performed to define a first alignment mark having a first direction portion orthogonal to a second direction portion. A second lithography process is performed to overlap a part of the first direction portion as well as a part of the second direction portion, thereby maintaining an exposed area of the first alignment mark having a first corresponding direction portion and a second corresponding direction portion. A first critical dimension of the first corresponding direction portion and a second critical dimension of the second corresponding direction portion are measured.

Abstract translation: 用于光刻和蚀刻工艺的监测方法包括以下步骤。 执行第一光刻处理和第一蚀刻处理以限定具有与第二方向部分正交的第一方向部分的第一对准标记。 执行第二光刻处理以与第一方向部分的一部分以及第二方向部分的一部分重叠，从而保持第一对准标记的暴露区域具有第一对应方向部分和第二对应方向部分。 测量第一对应方向部分的第一临界尺寸和第二对应方向部分的第二临界尺寸。

公开(公告)号：US20160336451A1

公开(公告)日：2016-11-17

申请号：US14741464

申请日：2015-06-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhen-Cyuan Li ,  Nan-Yuan Huang ,  Shui-Yen Lu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7853 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7851

Abstract: A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a spacer structure and a source/drain region. The fin structure is disposed on the substrate, the gate structure is disposed on the fin structure. The spacer structure is disposed on a sidewall of the gate structure. The spacer structure includes a first spacer with a first height and a second spacer with a second height, wherein the first spacer is disposed between the second spacer, and the first height is different from the second height. The source/drain region is disposed in a semiconductor layer at two sides of the spacer structure. The present invention further provides a method of forming the same.

Abstract translation: 提供非平面晶体管。 它包括衬底，翅片结构，栅极结构，间隔结构和源极/漏极区域。 翅片结构设置在基板上，栅极结构设置在翅片结构上。 间隔结构设置在栅极结构的侧壁上。 间隔结构包括具有第一高度的第一间隔件和具有第二高度的第二间隔件，其中第一间隔件设置在第二间隔件之间，第一高度不同于第二高度。 源极/漏极区域设置在间隔结构的两侧的半导体层中。 本发明还提供一种形成该方法的方法。

公开(公告)号：US09443952B2

公开(公告)日：2016-09-13

申请号：US14506009

申请日：2014-10-03

Applicant: United Microelectronics Corp.

Inventor： Chun-Tsen Lu ,  Chih-Jung Su ,  Jian-Wei Chen ,  Shui-Yen Lu ,  Yi-Wen Chen ,  Po-Cheng Huang ,  Chen-Ming Huang ,  Shih-Fang Tzou

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/0206 ,  H01L21/02065 ,  H01L21/02271 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/4966 ,  H01L29/517

Abstract: A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap between two adjacent fins. At least one first stacked structure is formed on one fin and at least one second stacked structure is formed on one insulation layer. A first dielectric layer is formed to cover the first and second stacked structures. A portion of the first dielectric layer and portions of the first and second stacked structures are removed. Another portion of the first dielectric layer is removed until a top of the remaining first dielectric layer is lower than tops of the first and second stacked structures. A second dielectric layer is formed to cover the first and second stacked structures. A portion of the second dielectric layer is removed until the tops of the first and second stacked structures are exposed.

Abstract translation: 公开了一种形成半导体器件的方法。 提供具有多个翅片的基板。 绝缘层填充两个相邻翅片之间的间隙的下部。 在一个翅片上形成至少一个第一堆叠结构，并且在一个绝缘层上形成至少一个第二堆叠结构。 形成第一电介质层以覆盖第一和第二堆叠结构。 去除第一电介质层的一部分和第一和第二堆叠结构的部分。 去除第一电介质层的另一部分，直到剩余的第一电介质层的顶部低于第一和第二堆叠结构的顶部。 形成第二电介质层以覆盖第一和第二堆叠结构。 去除第二电介质层的一部分直到第一和第二堆叠结构的顶部露出。