公开(公告)号：US20240234505A1

公开(公告)日：2024-07-11

申请号：US18105887

申请日：2023-02-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Kuang-Hsiu Chen ,  Shou-Hung Wu ,  Shao-Wei Wang ,  Yu-Ren Wang

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a fin structure disposed on a substrate, and an epitaxial semiconductor layer disposed over an upper part of the fin structure and having an undercut. The epitaxial semiconductor layer has a right-left symmetric, concave polygonal cross-section.

公开(公告)号：US20190221562A1

公开(公告)日：2019-07-18

申请号：US15880492

申请日：2018-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Yu-Ying Lin ,  Yen-Hsing Chen ,  Chun-Jen Chen ,  Chun-Wei Yu ,  Keng-Jen Lin ,  Yu-Ren Wang

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66545

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.

公开(公告)号：US20170309485A1

公开(公告)日：2017-10-26

申请号：US15137010

申请日：2016-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Chun-Wei Yu ,  Kuang-Hsiu Chen ,  Yi-Liang Ye ,  Hsu Ting ,  Neng-Hui Yang

IPC: H01L21/268 ,  H01L21/687 ,  H01L21/67 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/2686 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/67115 ,  H01L21/68785 ,  H01L29/0847 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7834

Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.

公开(公告)号：US09514993B2

公开(公告)日：2016-12-06

申请号：US14664933

申请日：2015-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Wei Yu ,  Ted Ming-Lang Guo ,  Hsu Ting ,  Yu-Ren Wang

IPC: H01L21/8238 ,  H01L21/283 ,  H01L21/308

CPC classification number: H01L21/823814 ,  H01L21/02236 ,  H01L21/283 ,  H01L21/3083 ,  H01L21/3085 ,  H01L21/31111 ,  H01L21/823425 ,  H01L21/823878

Abstract: A method for manufacturing semiconductor devices includes following steps. A substrate including a first gate structure and a second gate structure formed thereon is provided. The first gate structure and the second gate structure are complementary to each other. Next, a first mask layer covering the second gate structure is formed and followed by forming first recesses in the substrate at two respective sides of the first transistor. Then, forming the first recesses, a first epitaxial layer is formed in each first recess. After forming the first epitaxial layers, a local protecting cap is formed on the first epitaxial layers and followed by removing the first mask layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 提供了包括形成在其上的第一栅极结构和第二栅极结构的衬底。 第一栅极结构和第二栅极结构彼此互补。 接下来，形成覆盖第二栅极结构的第一掩模层，随后在第一晶体管的两个相应的两侧在衬底中形成第一凹槽。 然后，形成第一凹部，在每个第一凹部中形成第一外延层。 在形成第一外延层之后，在第一外延层上形成局部保护帽，然后除去第一掩模层。

公开(公告)号：US20160284601A1

公开(公告)日：2016-09-29

申请号：US14664933

申请日：2015-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Wei Yu ,  Ted Ming-Lang Guo ,  Hsu Ting ,  Yu-Ren Wang

IPC: H01L21/8238 ,  H01L21/308 ,  H01L21/283

CPC classification number: H01L21/823814 ,  H01L21/02236 ,  H01L21/283 ,  H01L21/3083 ,  H01L21/3085 ,  H01L21/31111 ,  H01L21/823425 ,  H01L21/823878

Abstract: A method for manufacturing semiconductor devices includes following steps. A substrate including a first gate structure and a second gate structure formed thereon is provided. The first gate structure and the second gate structure are complementary to each other. Next, a first mask layer covering the second gate structure is formed and followed by forming first recesses in the substrate at two respective sides of the first transistor. Then, forming the first recesses, a first epitaxial layer is formed in each first recess. After forming the first epitaxial layers, a local protecting cap is formed on the first epitaxial layers and followed by removing the first mask layer.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 提供了包括形成在其上的第一栅极结构和第二栅极结构的衬底。 第一栅极结构和第二栅极结构彼此互补。 接下来，形成覆盖第二栅极结构的第一掩模层，随后在第一晶体管的两个相应的两侧在衬底中形成第一凹槽。 然后，形成第一凹部，在每个第一凹部中形成第一外延层。 在形成第一外延层之后，在第一外延层上形成局部保护帽，然后除去第一掩模层。

公开(公告)号：US10559655B1

公开(公告)日：2020-02-11

申请号：US16210738

申请日：2018-12-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Chia-Ming Kuo ,  Fu-Jung Chuang ,  Chun-Wei Yu ,  Po-Jen Chuang ,  Yu-Ren Wang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/51 ,  H01L21/768 ,  H01L29/78 ,  H01L21/764

Abstract: A semiconductor device comprises at least one gate structure disposed on a substrate; a first dielectric layer disposed on the substrate and contacting an outer sidewall of the at least one gate structure; a second dielectric layer having a L shape disposed on the first dielectric layer and contacting the outer sidewall of the at least one gate structure; an etch stop layer contacting the second dielectric layer, the first dielectric layer and the substrate, wherein the second dielectric layer has an upper portion and a lower portion contacting the upper portion, the upper portion extends along the outer sidewall, the lower portion extends from the outer sidewall to the etch stop layer; and an air gap between the second dielectric layer and the etch stop layer; wherein the first dielectric layer and the lower portion of the second dielectric layer have a same width.

公开(公告)号：US20190006172A1

公开(公告)日：2019-01-03

申请号：US15639381

申请日：2017-06-30

Applicant: United Microelectronics Corp.

Inventor： Hsu Ting ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Keng-Jen Lin ,  Yu-Ren Wang

IPC: H01L21/02

Abstract: A method for processing a semiconductor device is provided. The semiconductor device includes a protruding structure on a substrate, the protruding structure having a nitride spacer at a sidewall, and an epitaxial layer is formed in the substrate adjacent to the protruding structure. The method includes removing the nitride spacer on the protruding structure. Then, a dilute hydrofluoric (DHF) cleaning process is performed over the substrate, wherein a top surficial portion of the epitaxial layer is removed. A standard clean (SC) process is performed over the substrate, wherein a native oxide layer is formed on an expose surface of the epitaxial layer.

公开(公告)号：US09966266B2

公开(公告)日：2018-05-08

申请号：US15137010

申请日：2016-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Chun-Wei Yu ,  Kuang-Hsiu Chen ,  Yi-Liang Ye ,  Hsu Ting ,  Neng-Hui Yang

IPC: H01L21/02 ,  H01L21/268 ,  H01L21/67 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/687 ,  H01L29/66

CPC classification number: H01L21/2686 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/67115 ,  H01L21/68785 ,  H01L29/0847 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7834

Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.

公开(公告)号：US09646889B1

公开(公告)日：2017-05-09

申请号：US15003782

申请日：2016-01-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Wei Yu ,  Hsu Ting ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Kuang-Hsiu Chen

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L29/7845 ,  H01L21/02065 ,  H01L21/28123 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure on the substrate and a first spacer adjacent to the first gate structure; forming a first epitaxial layer in the substrate adjacent to the first gate structure; forming a first hard mask layer on the first gate structure; removing part of the first hard mask layer to form a protective layer on the first epitaxial layer; and removing the remaining first hard mask layer.