公开(公告)号：US09666680B1

公开(公告)日：2017-05-30

申请号：US14944224

申请日：2015-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Hsiang Chang ,  Shen-De Wang ,  Chih-Chien Chang ,  Jianjun Yang ,  Aaron Chen

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/265 ,  H01L21/321 ,  H01L21/223 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/51 ,  H01L27/11521

CPC classification number: H01L29/42328 ,  H01L21/26586 ,  H01L21/28273 ,  H01L21/28562 ,  H01L21/31111 ,  H01L21/321 ,  H01L21/32133 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/788

Abstract: A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.

公开(公告)号：US20160049525A1

公开(公告)日：2016-02-18

申请号：US14462550

申请日：2014-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Weichang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wei Ta ,  Yi-Shan Chiu ,  Yuan-Hsiang Chang

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/31105 ,  H01L21/31144 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.

Abstract translation: 闪速存储器结构包括衬底上的存储栅极，与存储栅极相邻的选择栅极以及存储栅极和选择栅极之间的氧化物氮化物间隔物，其中氧化物氮化物间隔物还包括氧化物层和氮化物 层具有上部氮化物部分和下部氮化物部分，并且上部氮化物部分比下部氮化物部分薄。

公开(公告)号：US09660106B2

公开(公告)日：2017-05-23

申请号：US14462550

申请日：2014-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Weichang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wei Ta ,  Yi-Shan Chiu ,  Yuan-Hsiang Chang

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11573 ,  H01L21/311

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/31105 ,  H01L21/31144 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.

公开(公告)号：US20160172200A1

公开(公告)日：2016-06-16

申请号：US14569794

申请日：2014-12-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WEICHANG LIU ,  ZHEN CHEN ,  Shen-De Wang ,  Wei Ta ,  Yi-Shan Chiu ,  Yuan-Hsiang Chang ,  Chih-Chien Chang

IPC: H01L21/28

CPC classification number: H01L29/40117 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for fabricating non-volatile memory device is disclosed. The method includes the steps of: providing a substrate having a stack structure thereon; performing a first oxidation process to form a first oxide layer on the substrate and the stack structure; etching the first oxide layer for forming a first spacer adjacent to the stack structure; performing a second oxidation process to form a second oxide layer on the substrate; forming a dielectric layer on the first spacer and the second oxide layer; and etching the dielectric layer for forming a second spacer.

Abstract translation: 公开了一种用于制造非易失性存储器件的方法。 该方法包括以下步骤：提供其上具有堆叠结构的衬底; 执行第一氧化工艺以在衬底和堆叠结构上形成第一氧化物层; 蚀刻用于形成邻近堆叠结构的第一间隔物的第一氧化物层; 执行第二氧化工艺以在所述衬底上形成第二氧化物层; 在所述第一间隔物和所述第二氧化物层上形成介电层; 并蚀刻用于形成第二间隔物的电介质层。

公开(公告)号：US20160163722A1

公开(公告)日：2016-06-09

申请号：US14596227

申请日：2015-01-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Hsiang Chang ,  Aaron Chen ,  JIANJUN YANG ,  Chih-Chien Chang

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/321 ,  H01L21/28 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/788 ,  H01L29/423

CPC classification number: H01L27/11521 ,  H01L27/11534 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788

Abstract: A non-volatile memory cell includes a substrate, an erase gate disposed on the substrate and having a top plane, two floating gates disposed respectively at both sides of the erase gate, two control gates disposed respectively on two floating gates, and two select gates disposed respectively at outer sides of the two floating gates, where the two select gates have tilted top planes which are symmetric to each other.

Abstract translation: 非易失性存储单元包括衬底，设置在衬底上的擦除栅极，具有顶面，分别设置在擦除栅极两侧的两个浮置栅极，分别设置在两个浮置栅极上的两个控制栅极和两个选择栅极 分别设置在两个浮动栅极的外侧，其中两个选择栅极具有彼此对称的倾斜顶部平面。

公开(公告)号：US20160042957A1

公开(公告)日：2016-02-11

申请号：US14454332

申请日：2014-08-07

Applicant: United Microelectronics Corp.

Inventor： Yuan-Hsiang Chang ,  Yi-Shan Chiu ,  Zhen Chen ,  Wei Ta ,  Wei-Chang Liu

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L21/28282 ,  H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned charge-trapping layer is formed on the substrate, covering the memory area and the second device area but exposing the first device area. A first gate oxide layer is formed in the first device area. The charge-trapping layer in the second device area is removed. A second gate oxide layer is formed in the second device area.

Abstract translation: 描述半导体工艺。 提供具有存储区域，第一设备区域和第二设备区域的半导体衬底。 图案化的电荷捕获层形成在衬底上，覆盖存储区域和第二器件区域，但暴露第一器件区域。 第一栅极氧化物层形成在第一器件区域中。 去除第二装置区域中的电荷捕获层。 第二栅极氧化层形成在第二器件区域中。