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公开(公告)号：US12193337B2
公开(公告)日：2025-01-07
申请号：US16991055
申请日：2020-08-12
Applicant: Winbond Electronics Corp.
Inventor： Wen-Chia Ou , Chih-Chao Huang , Min-Chih Wei , Yu-Ting Chen , Chi-Ching Liu
Abstract: A method of fabricating a semiconductor device includes the following steps. A plurality of doped regions are formed in a substrate. A first dielectric layer is formed on the substrate. A plurality of first contacts and second contacts are formed in the first dielectric layer to be connected to the plurality of doped regions. A memory element is formed on the first dielectric layer. The memory element is electrically connected to the second contact. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer surrounds the memory element. A conductive line is formed in the second dielectric layer. A top surface of the conductive line is at a same level as a top surface of the memory element, and the conductive line is electrically connected to the plurality of first contacts.
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公开(公告)号：US11908516B2
公开(公告)日：2024-02-20
申请号：US17458559
申请日：2021-08-27
Applicant: Winbond Electronics Corp.
Inventor： Ming-Che Lin , Min-Chih Wei , Ping-Kun Wang , Yu-Ting Chen , Chih-Cheng Fu , Chang-Tsung Pai
CPC classification number: G11C13/0038 , G11C13/004 , G11C13/0026 , G11C13/0028 , G11C2213/79
Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
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公开(公告)号：US20230129196A1
公开(公告)日：2023-04-27
申请号：US18087802
申请日：2022-12-22
Applicant: Winbond Electronics Corp.
Inventor： Chi-Ching Liu , Yu-Ting Chen , Chang-Tsung Pai , Shun-Li Lan , Yen-De Lee , Chih-Jung Ni
IPC: H01L21/768 , H10B99/00
Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.
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公开(公告)号：US11152566B2
公开(公告)日：2021-10-19
申请号：US16709863
申请日：2019-12-10
Applicant: Winbond Electronics Corp.
Inventor： Po-Yen Hsu , Bo-Lun Wu , Ping-Kun Wang , Ming-Che Lin , Yu-Ting Chen , Chang-Tsung Pai , Shao-Ching Liao , Chi-Ching Liu
IPC: H01L45/00
Abstract: A resistive random access memory including first and second electrodes, a resistance variable layer, first and second metal layers and a resistance stabilizing layer is provided. The second electrode is disposed on the first electrode. The resistance variable layer is disposed between the first and second electrodes. The first metal layer is disposed between the resistance variable layer and the second electrode. The second metal layer is disposed between the first metal layer and the second electrode. The resistance stabilizing layer is disposed between the first and second metal layers. The oxygen content of the resistance variable layer is higher than that of the first metal layer, the oxygen content of the first metal layer is higher than that of the resistance stabilizing layer, the oxygen content of the resistance stabilizing layer is higher than that of the second metal layer.
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公开(公告)号：US20210287934A1
公开(公告)日：2021-09-16
申请号：US16817572
申请日：2020-03-12
Applicant: Winbond Electronics Corp.
Inventor： Chi-Ching Liu , Yu-Ting Chen , Chang-Tsung Pai , Shun-Li Lan , Yen-De Lee , Chih-Jung Ni
IPC: H01L21/768 , H01L21/8239
Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.
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Patent Agency Ranking
公开(公告)号：US11758740B2
公开(公告)日：2023-09-12
申请号：US17224152
申请日：2021-04-07
Applicant: Winbond Electronics Corp.
Inventor： Chang-Tsung Pai , Chiung-Lin Hsu , Yu-Ting Chen , Ming-Che Lin , Chi-Ching Liu
CPC classification number: H10B63/30 , H10N70/011 , H10N70/253 , H10N70/8265 , H10N70/841
Abstract: A three-dimensional semiconductor device includes multiple semiconductor device layers on a substrate, wherein each layer includes a first stacked structure, a first gate dielectric layer, a first semiconductor layer, a first channel layer, a first source region, a first drain region, and a first resistive random access memory cell. The first stacked structure on the substrate includes a first insulating layer and a first gate conductor layer. The first gate dielectric layer surrounds a sidewall of the first stacked structure. The first semiconductor layer surrounds a sidewall of the first gate dielectric layer. The first channel layer is in the first semiconductor layer. The first source region and the first drain region are on both sides of the first channel layer in the first semiconductor layer. The first resistive random access memory cell is on a first sidewall of the first semiconductor layer and connected to the first drain region.
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公开(公告)号：US11620500B2
公开(公告)日：2023-04-04
申请号：US15868392
申请日：2018-01-11
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao , Chih-Cheng Fu , Ming-Che Lin , Yu-Ting Chen , Seow-Fong (Dennis) Lim
Abstract: A synapse system is provided which includes three transistors and a resistance-switching element arranged between two neurons. The resistance-switching element has a resistance value and it is arranged between two neurons. A first transistor is connected between the resistance-switching element and one of the neurons. A second transistor and a third transistor are arranged between the two neurons, and are connected in series which interconnects with the gate of the first transistor. A first input signal is transmitted from one of the neurons to the other neuron through the first transistor. A second input signal is transmitted from one of the neurons to the other neuron through the second transistor and the third transistor. The resistance value of the resistance-switching element is changed based on the time difference between the first input signal and the second input signal.
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公开(公告)号：US20210366986A1
公开(公告)日：2021-11-25
申请号：US17224152
申请日：2021-04-07
Applicant: Winbond Electronics Corp.
Inventor： Chang-Tsung Pai , Chiung-Lin Hsu , Yu-Ting Chen , Ming-Che Lin , Chi-Ching Liu
Abstract: A three-dimensional semiconductor device includes multiple semiconductor device layers on a substrate, wherein each layer includes a first stacked structure, a first gate dielectric layer, a first semiconductor layer, a first channel layer, a first source region, a first drain region, and a first resistive random access memory cell. The first stacked structure on the substrate includes a first insulating layer and a first gate conductor layer. The first gate dielectric layer surrounds a sidewall of the first stacked structure. The first semiconductor layer surrounds a sidewall of the first gate dielectric layer. The first channel layer is in the first semiconductor layer. The first source region and the first drain region are on both sides of the first channel layer in the first semiconductor layer. The first resistive random access memory cell is on a first sidewall of the first semiconductor layer and connected to the first drain region.
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公开(公告)号：US20190221260A1
公开(公告)日：2019-07-18
申请号：US16181372
申请日：2018-11-06
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Shao-Ching Liao , Yu-Ting Chen , Ming-Che Lin , Chien-Min Wu , Chia-Hua Ho
IPC: G11C13/00
CPC classification number: G11C13/0038 , G11C13/0004 , G11C13/004 , G11C13/0064 , G11C2013/0045
Abstract: A power on reset method for a resistive memory storage device is provided and includes performing a forming procedure on a memory cell of the resistive memory storage device. The forming procedure includes applying at least one forming voltage and at least one reset voltage to the memory cell. The forming procedure further includes a thermal step. The step of applying at least one reset voltage to the memory cell may be preformed before or after the thermal step. After one forming voltage is applied, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. After the thermal step, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. In addition, after one reset voltage is applied, if the memory cell passes verification, the next reset voltage is not applied to the memory cell.
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公开(公告)号：US12087619B2
公开(公告)日：2024-09-10
申请号：US18087802
申请日：2022-12-22
Applicant: Winbond Electronics Corp.
Inventor： Chi-Ching Liu , Yu-Ting Chen , Chang-Tsung Pai , Shun-Li Lan , Yen-De Lee , Chih-Jung Ni
IPC: H01L21/768 , H10B99/00
CPC classification number: H01L21/76816 , H10B99/00
Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.
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