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公开(公告)号：US08084869B2
公开(公告)日：2011-12-27
申请号：US12478837
申请日：2009-06-05
IPC分类号： H01L23/29
CPC分类号： H01L23/49838 , H01L21/563 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/13144 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48105 , H01L2224/48227 , H01L2224/48229 , H01L2224/73204 , H01L2224/73253 , H01L2224/81203 , H01L2224/81801 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H05K1/112 , H05K3/4652 , H05K2201/09227 , H05K2201/099 , H05K2201/10734 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A technique permitting the reduction in size of a semiconductor device is provided. In a BGA type semiconductor device with a semiconductor chip flip-chip-bonded onto a wiring substrate, bump electrodes of the semiconductor chip are coupled to lands formed at an upper surface of the wiring substrate. The lands at the upper surface of the wiring substrate are coupled electrically to solder balls formed on a lower surface of the wiring substrate. Therefore, the lands include first type lands with lead-out lines coupled thereto and second type lands with lead-out lines not coupled thereto but with vias formed just thereunder. The lands are arrayed in six or more rows at equal pitches in an advancing direction of the rows. However, a row-to-row pitch is not made an equal pitch. In land rows which are likely to cause a short-circuit, the pitch between adjacent rows is made large, while in land rows which are difficult to cause a short-circuit, the pitch between adjacent rows is made small. By so doing, both prevention of a short-circuit and improvement of the layout density of lands are attained at a time.
摘要翻译： 提供了允许半导体器件的尺寸减小的技术。 在具有倒装芯片接合在布线基板上的半导体芯片的BGA型半导体器件中，半导体芯片的突起电极被耦合到在布线基板的上表面上形成的焊盘。 布线基板的上表面的焊盘电连接到形成在布线基板的下表面上的焊球。 因此，焊盘包括具有与其耦合的引出线的第一类型的焊盘和没有耦合到其上的导出线，但是具有刚好形成的通孔的第二类型的焊盘。 焊盘沿着行的前进方向以等间距排列成六行或更多行。 然而，行到行间距不是相等的音高。 在可能导致短路的陆地列中，相邻行之间的间距变大，而在难以引起短路的陆地行中，相邻行之间的间距变小。 通过这样做，一次可以实现防止短路的改善和布局密度的提高。
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公开(公告)号：US07855593B2
公开(公告)日：2010-12-21
申请号：US12497982
申请日：2009-07-06
CPC分类号： G11C5/147
摘要： A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed. The second circuit block has an input unit which receives signals supplied from the first circuit block, and the input unit of the second circuit block has an input circuit which, in accordance with a control signal sent from said third circuit block to said second circuit block, causes a specific signal level to be maintained in compliance with the operating voltage of the second circuit block irrespective of the signal supplied from the first circuit block when the third circuit block instructs the second power supply state to the first circuit block.
摘要翻译： 提供一种在实现多功能化和省电的同时提高设计效率的半导体集成电路装置。 半导体集成电路装置具有第一至第三电路块，并且被置于第一电源状态，其中根据来自第三电路块或第二电源的指令保证第一电路块中的内部电路的操作 不能保证内部电路的运行状态。 第二电路块具有接收从第一电路块提供的信号的输入单元，并且第二电路块的输入单元具有输入电路，该输入电路根据从所述第三电路块发送到所述第二电路块的控制信号 当第三电路块向第一电路块指示第二电源状态时，使得与第二电路块的工作电压保持一定的特定信号电平，而与第一电路块所提供的信号无关。
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公开(公告)号：US07821814B2
公开(公告)日：2010-10-26
申请号：US12222753
申请日：2008-08-15
CPC分类号： G11C11/417 , G11C5/14 , G11C5/148
摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
摘要翻译： 当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗 同时存储数据增加。 因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。
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公开(公告)号：US07786585B2
公开(公告)日：2010-08-31
申请号：US12188591
申请日：2008-08-08
申请人： Takako Funakoshi , Eiichi Murakami , Kazumasa Yanagisawa , Kan Takeuchi , Hideo Aoki , Hizuru Yamaguchi , Takayuki Oshima , Kazuyuki Tsunokuni , Kousuke Okuyama
发明人： Takako Funakoshi , Eiichi Murakami , Kazumasa Yanagisawa , Kan Takeuchi , Hideo Aoki , Hizuru Yamaguchi , Takayuki Oshima , Kazuyuki Tsunokuni , Kousuke Okuyama
CPC分类号： H01L23/53238 , H01L21/823871 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.
摘要翻译： 在具有多层埋地布线的半导体集成电路装置中，旨在防止在其底部连接到埋地布线的插头与埋地布线之间的界面处的应力迁移引起的不连续性的发生。 例如，在第一Cu布线的宽度不小于约0.9μm且小于约1.44μm的情况下，并且第二Cu布线的宽度和塞子的直径为约0.18μm的情况下，存在 布置两个或更多个将第一布线和第二铜布线彼此电连接的插头。
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公开(公告)号：US20090267686A1
公开(公告)日：2009-10-29
申请号：US12497982
申请日：2009-07-06
CPC分类号： G11C5/147
摘要： A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed. The second circuit block has an input unit which receives signals supplied from the first circuit block, and the input unit of the second circuit block has an input circuit which, in accordance with a control signal sent from said third circuit block to said second circuit block, causes a specific signal level to be maintained in compliance with the operating voltage of the second circuit block irrespective of the signal supplied from the first circuit block when the third circuit block instructs the second power supply state to the first circuit block.
摘要翻译： 提供一种在实现多功能化和省电的同时提高设计效率的半导体集成电路装置。 半导体集成电路装置具有第一至第三电路块，并且被置于第一电源状态，其中根据来自第三电路块或第二电源的指令保证第一电路块中的内部电路的操作 不能保证内部电路的运行状态。 第二电路块具有接收从第一电路块提供的信号的输入单元，并且第二电路块的输入单元具有输入电路，该输入电路根据从所述第三电路块发送到所述第二电路块的控制信号 当第三电路块向第一电路块指示第二电源状态时，使得与第二电路块的工作电压保持一定的特定信号电平，而与第一电路块所提供的信号无关。
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公开(公告)号：US07414909B2
公开(公告)日：2008-08-19
申请号：US11606025
申请日：2006-11-30
IPC分类号： G11C7/02
摘要： There is provided a high-density mask ROM operable at a high speed. With the mask ROM, respective source lines are disposed so as to be shared by memory cells in respective columns adjacent to each other, and bit lines are disposed so as to correspond to the respective columns of the memory cells. Further, the dummy cells are disposed for the respective columns of the memory cells. The dummy cells are each made up of a series-circuit including a first switching transistor that is turned into the conducting state in response to a signal potential on a dummy word line (DWL), and a second switching transistor 17 for coupling an adjacent source line to the bit line corresponding thereto in response to a potential of the source line in a column corresponding thereto. The memory cells each are made up of one unit of a transistor and a data storage formed by mask wiring. At the time of reading data, a potential of the source line in a select column is caused to undergo a change, whereupon there occurs a potential difference between a pair made up of the bit line as selected to which the memory cells as selected are coupled, and a reference bit line with the dummy cells coupled thereto, so that it is possible to execute readout of data by detecting the potential difference.
摘要翻译： 提供了可高速操作的高密度掩模ROM。 利用掩模ROM，各个源极线被布置成由彼此相邻的各个列中的存储单元共享，并且位线被布置为与存储单元的各个列对应。 此外，为存储单元的各列设置虚设单元。 虚拟单元各自由串联电路组成，串联电路包括响应于虚拟字线（DWL）上的信号电位而变为导通状态的第一开关晶体管，以及用于耦合相邻源极的第二开关晶体管17 响应于与其对应的列中的源极线的电位，对应于其的位线。 每个存储单元由晶体管的一个单元和由掩模布线形成的数据存储器构成。 在读取数据时，使选择列中的源极线的电位发生变化，由此选择由选择的存储器单元所耦合的位线组成的一对之间存在电位差 以及与其耦合的虚拟单元的参考位线，使得可以通过检测电位差来执行数据的读出。
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公开(公告)号：US07411267B2
公开(公告)日：2008-08-12
申请号：US11048909
申请日：2005-02-03
IPC分类号： H01L29/00
CPC分类号： H01L27/0207 , H01L23/5223 , H01L24/06 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2924/13091 , H01L2924/14 , H01L2924/3011 , H03K17/6871 , H03K19/0016 , H01L2924/00014 , H01L2924/00
摘要： The invention provides a semiconductor integrated circuit device with improved designing efficiency while achieving higher functions. An inner circuit is surrounded by a plurality of cells in which a first switch element for connecting a power supply voltage line or a ground voltage supply line to a power supply line of an internal circuit is disposed below power supply lines extending in a first and second directions, and the power lines are connected together.
摘要翻译： 本发明提供一种提高设计效率同时实现更高功能的半导体集成电路器件。 内部电路被多个单元包围，其中用于将电源电压线或接地电压供给线连接到内部电路的电源线的第一开关元件设置在第一和第二电极中延伸的电源线之下 方向，电源线连接在一起。
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公开(公告)号：US07254680B2
公开(公告)日：2007-08-07
申请号：US11641808
申请日：2006-12-20
申请人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
发明人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
CPC分类号： G11C7/1006 , G06F12/0215 , G06F12/0893 , G06F13/161 , G06F2212/3042 , G11C7/065 , G11C11/4091 , G11C11/4093 , G11C2207/104 , G11C2207/2245
摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.
摘要翻译： 为了提高第一次访问的速度（从先前访问的字线读取访问）到多存储体存储器，使用多存储体存储器宏结构。 数据保存在每个存储体的读出放大器中。 当对保持的数据进行访问时，输出由读出放大器锁存的数据，从而提高对存储器宏结构的首次访问的速度。 即，使每个存储体用作读出放大器高速缓存。 为了更好地提高这种感测放大器高速缓存的命中率，访问控制器在访问存储器宏结构之后自我预取下一个地址（已经添加了预定偏移量的地址），以便自我预取中的数据 地址由另一个存储体中的读出放大器预读。
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公开(公告)号：US20070127302A1
公开(公告)日：2007-06-07
申请号：US11606025
申请日：2006-11-30
IPC分类号： G11C7/02
摘要： There is provided a high-density mask ROM operable at a high speed. With the mask ROM, respective source lines are disposed so as to be shared by memory cells in respective columns adjacent to each other, and bit lines are disposed so as to correspond to the respective columns of the memory cells. Further, the dummy cells are disposed for the respective columns of the memory cells. The dummy cells are each made up of a series-circuit including a first switching transistor that is turned into the conducting state in response to a signal potential on a dummy word line (DWL), and a second switching transistor 17 for coupling an adjacent source line to the bit line corresponding thereto in response to a potential of the source line in a column corresponding thereto. The memory cells each are made up of one unit of a transistor and a data storage formed by mask wiring. At the time of reading data, a potential of the source line in a select column is caused to undergo a change, whereupon there occurs a potential difference between a pair made up of the bit line as selected to which the memory cells as selected are coupled, and a reference bit line with the dummy cells coupled thereto, so that it is possible to execute readout of data by detecting the potential difference.
摘要翻译： 提供了可高速操作的高密度掩模ROM。 利用掩模ROM，各个源极线被布置成由彼此相邻的各个列中的存储单元共享，并且位线被布置为与存储单元的各个列对应。 此外，为存储单元的各列设置虚设单元。 虚拟单元各自由串联电路组成，串联电路包括响应于虚拟字线（DWL）上的信号电位而变为导通状态的第一开关晶体管，以及用于耦合相邻源极的第二开关晶体管17 响应于与其对应的列中的源极线的电位，对应于其的位线。 每个存储单元由晶体管的一个单元和由掩模布线形成的数据存储器构成。 在读取数据时，使选择列中的源极线的电位发生变化，由此选择由所选择的存储器单元耦合到的位线构成的一对之间存在电位差 以及与其耦合的虚拟单元的参考位线，使得可以通过检测电位差来执行数据的读出。
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公开(公告)号：US06787835B2
公开(公告)日：2004-09-07
申请号：US10167754
申请日：2002-06-11
申请人： Bryan Atwood , Kazuo Yano , Tomoyuki Ishii , Taro Osabe , Kazumasa Yanagisawa , Takeshi Sakata
发明人： Bryan Atwood , Kazuo Yano , Tomoyuki Ishii , Taro Osabe , Kazumasa Yanagisawa , Takeshi Sakata
IPC分类号： H01L27108
CPC分类号： H01L27/105 , G11C11/405 , G11C11/406 , G11C11/4076 , G11C2207/2281 , G11C2207/229 , H01L27/0207 , H01L27/108 , H01L27/1203
摘要： A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two- and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.
摘要翻译： 本发明提供了高集成度的动态随机存取存储器。 此外，提供了一种写入方法，使得减少了双晶体管和三晶体管增益单元存储器的单元尺寸。 一种结合了作为写入元件的薄沟道晶体管的动态存储器，使得在本发明的存储器件中实现长的数据存储保持。 通过本发明也实现了具有低操作功率和高密度的动态存储单元。
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