公开(公告)号：US4336465A

公开(公告)日：1982-06-22

申请号：US61252

申请日：1979-07-27

申请人： Masao Nakano ,  Yoshihiro Takemae ,  Katsuhiko Kabashima

发明人： Masao Nakano ,  Yoshihiro Takemae ,  Katsuhiko Kabashima

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C7/20 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/417 ,  G11C11/419 ,  H03K3/356 ,  H03K5/00

CPC分类号： G11C11/4093 ,  G11C7/1048 ,  G11C7/20 ,  H03K3/356095

摘要： A reset circuit used for resetting, for example a memory device after a reading-out from a memory is effected, comprises fist and second reset transistors, for connecting first and second circuits to a common voltage source, and a short-circuit transistor, having a lower threshold voltage than the threshold voltage of said first and second reset transistors, for connecting said first and second circuits when said short circuit transistor receives the same input signal as supplied to said first and second reset transistors.

摘要翻译： 用于复位的复位电路，例如在从存储器读出数据之后，存储器件包括用于将第一和第二电路连接到公共电压源的第一和第二复位晶体管，以及短路晶体管，具有 比所述第一和第二复位晶体管的阈值电压低的阈值电压，用于当所述短路晶体管接收与提供给所述第一和第二复位晶体管相同的输入信号时连接所述第一和第二电路。

公开(公告)号：US4156939A

公开(公告)日：1979-05-29

申请号：US908836

申请日：1978-05-23

申请人： Yoshihiro Takemae ,  Takeo Tatematsu ,  Katsuhiko Kabashima ,  Tomio Nakano ,  Kiyoshi Miyasaka

发明人： Yoshihiro Takemae ,  Takeo Tatematsu ,  Katsuhiko Kabashima ,  Tomio Nakano ,  Kiyoshi Miyasaka

IPC分类号： G11C5/02 ,  G11C7/02 ,  G11C11/404 ,  G11C11/407 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  G11C11/40

CPC分类号： G11C11/404 ,  G11C11/407 ,  G11C5/025 ,  H01L27/088 ,  H01L27/10805 ,  H01L27/105

摘要： An integrated semiconductor memory device is formed on a semiconductor substrate of one conductivity type on which there are provided peripheral circuits consisting of a pluality of memory cells each containing a storage capacitor and an IG FET. The IG FET in each memory cell acts as a transfer gate which is disposed on a surface region having the same conductivity type as that of the substrate and higher impurity concentrations than that of the substrate. The transfer gate has a gate threshold value which is higher than that of the IG FET in the peripheral circuits and which is insensitive to a noise pulse supplied thereto, whereby the destruction of data by noise pulse can be effectively prevented.

摘要翻译： 集成半导体存储器件形成在一种导电类型的半导体衬底上，其中提供由包含存储电容器和IG FET的存储单元的pluality组成的外围电路。 每个存储单元中的IG FET用作传输门，其布置在具有与衬底相同的导电类型的表面区域上，并且具有比衬底更高的杂质浓度。 传输门具有比周边电路中的IG FET高的栅极阈值，并且对提供给其的噪声脉冲不敏感，从而可以有效地防止数据噪声脉冲的破坏。

公开(公告)号：US4511997A

公开(公告)日：1985-04-16

申请号：US439507

申请日：1982-11-05

申请人： Shigeki Nozaki ,  Yoshihiro Takemae ,  Tomio Nakano

发明人： Shigeki Nozaki ,  Yoshihiro Takemae ,  Tomio Nakano

IPC分类号： G11C11/419 ,  G11C11/34 ,  G11C11/401 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/40

CPC分类号： G11C11/4096

摘要： A metal-insulator semiconductor dynamic memory device including sense amplifiers arrayed on a semiconductor substrate and divided into a plurality of sense amplifier groups. Column decoders are provided, one decoder for each sense amplifier group, each sense amplifier group being selected by the column decoder. One or more control signal lines for simultaneously selecting the output signals of at least two sense amplifiers in the sense amplifier group selected by the column decoder, a plurality of data buses for transferring the output signals of at least two sense amplifiers selected by one or more control signal lines, are included in the memory device. All of the sense amplifiers have the control signal lines and the data buses in common.

摘要翻译： 一种金属绝缘体半导体动态存储器件，包括排列在半导体衬底上并分成多个读出放大器组的读出放大器。 提供列解码器，每个读出放大器组的一个解码器，每个读出放大器组由列解码器选择。 一个或多个控制信号线，用于同时选择由列解码器选择的读出放大器组中的至少两个读出放大器的输出信号;多个数据总线，用于传送由一个或多个选择的至少两个读出放大器的输出信号 控制信号线被包括在存储器件中。 所有的读出放大器都具有控制信号线和数据总线。

公开(公告)号：US4970693A

公开(公告)日：1990-11-13

申请号：US484474

申请日：1990-02-23

申请人： Shigeki Nozaki ,  Tsuyoshi Ohira ,  Masaru Satoh ,  Tomio Nakano ,  Yoshihiro Takemae

发明人： Shigeki Nozaki ,  Tsuyoshi Ohira ,  Masaru Satoh ,  Tomio Nakano ,  Yoshihiro Takemae

IPC分类号： G11C11/409 ,  G11C7/22 ,  G11C8/18 ,  G11C11/40 ,  G11C11/413

CPC分类号： G11C7/22 ,  G11C8/18

摘要： A semiconductor memory device is connected to a power source and includes a reference potential line connected to receive a reference potential from the power source. An input circuit is connected to the reference potential line and receives an external input signal having a logic level defined in reference to the reference potential to be supplied to the source potential line. The output circuit has an external output terminal which is connected to the reference potential line. The output circuit is for generating an output to the external output terminal. An inhibiting circuit inhibits a response to the external input signal of the input circuit for a predetermined period during which the output of the output circuit changes.

摘要翻译： 半导体存储器件连接到电源，并且包括连接以从电源接收参考电位的参考电位线。 输入电路连接到参考电位线，并接收具有参考参考电位定义的逻辑电平的外部输入信号以提供给源极电位线。 输出电路具有连接到参考电位线的外部输出端子。 输出电路用于产生到外部输出端子的输出。 禁止电路在输出电路的输出变化的预定时间段期间阻止对输入电路的外部输入信号的响应。

公开(公告)号：US4546457A

公开(公告)日：1985-10-08

申请号：US439591

申请日：1982-11-05

申请人： Shigeki Nozaki ,  Yoshihiro Takemae

发明人： Shigeki Nozaki ,  Yoshihiro Takemae

IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  G11C11/40

CPC分类号： G11C11/4087 ,  G11C7/06

摘要： A metal-insulator semiconductor dynamic memory device comprising sense amplifiers arrayed on a semiconductor substrate and column decoders. Each of the column decode being provided for a plurality of sense amplifiers and selecting one or more sense amplifiers from the plurality of sense amplifiers, the column decoders being dispersed on both sides of the arrayed sense amplifiers. A plurality of control signal lines which, in order to select the sense amplifiers, control gate elements connected between bit lines connected to the sense amplifiers and data bus lines and which are disposed on both sides of the arrayed sense amplifiers. Conducting lines are also disposed between the sense amplifiers and deliver signals from the control signal lines, for selecting sense amplifiers to the gate elements on the opposite side of the control signal lines with regard to the arrayed sense amplifiers.

摘要翻译： 包括排列在半导体衬底和列解码器上的读出放大器的金属 - 绝缘体半导体动态存储器件。 每个列解码被提供给多个读出放大器并且从多个读出放大器中选择一个或多个感测放大器，列解码器分散在排列的读出放大器的两侧。 多个控制信号线，为了选择读出放大器，控制栅极元件连接在连接到读出放大器的位线和数据总线之间，并且布置在阵列读出放大器的两侧。 传导线还设置在感测放大器之间并且传送来自控制信号线的信号，用于选择感测放大器到控制信号线相对于阵列读出放大器的相反侧的门元件。

公开(公告)号：US4771407A

公开(公告)日：1988-09-13

申请号：US79061

申请日：1987-07-29

申请人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Masao Nakano ,  Kimiaki Sato ,  Hatsuo Miyahara ,  Nobumi Kodama ,  Makoto Yanagisawa ,  Yasuhiro Takada ,  Satoshi Momozono

发明人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Masao Nakano ,  Kimiaki Sato ,  Hatsuo Miyahara ,  Nobumi Kodama ,  Makoto Yanagisawa ,  Yasuhiro Takada ,  Satoshi Momozono

IPC分类号： H03K3/353 ,  G01R31/28 ,  G11C11/401 ,  G11C29/46 ,  G11C11/40

CPC分类号： G11C29/46

摘要： In a semiconductor integrated circuit having first and second power supply lines for receiving a power supply voltage, an external input terminal for receiving an input signal, and a high voltage detection circuit for detecting at the external input terminal a high voltage higher than a predetermined voltage which is higher than the power supply voltage, the high voltage detection circuit comprises an input circuit connected to the external input terminal for generating circuit for generating a reference voltage; and a differential voltage amplifier connected to receive the detection voltage and the reference voltage for amplifying the difference between the detection voltage and the reference voltage, to thereby determine whether the high voltage is applied, the input circuit comprising; a level shift element connected to the external input terminal for providing the detection voltage; an impedance element connected between the level shift element and the second power supply line; and a leak current compensating element connected between the first power supply line and the level shift element for allowing a current to flow from the first power supply line through the leak current compensating element and the impedance element to the second power supply line when the high voltage is not applied to the external input terminal.

摘要翻译： 在具有用于接收电源电压的第一和第二电源线，用于接收输入信号的外部输入端子和用于在外部输入端子处检测高于预定电压的高电压的高电压检测电路的半导体集成电路中， 高电压检测电路包括连接到外部输入端的输入电路，用于产生用于产生参考电压的电路; 连接的差分电压放大器，用于接收检测电压和参考电压，用于放大检测电压和参考电压之间的差值，从而确定是否施加高电压，输入电路包括： 连接到所述外部输入端子以提供所述检测电压的电平移动元件; 连接在电平移位元件和第二电源线之间的阻抗元件; 以及泄漏电流补偿元件，其连接在所述第一电源线和所述电平移动元件之间，用于当高电压时允许电流从所述第一电源线流过所述漏电流补偿元件和所述阻抗元件流到所述第二电源线 不适用于外部输入端子。

公开(公告)号：US4583204A

公开(公告)日：1986-04-15

申请号：US452436

申请日：1982-12-23

申请人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsuyoshi Ohira

发明人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsuyoshi Ohira

IPC分类号： G11C11/401 ,  G11C11/4072 ,  G11C11/409 ,  G11C11/417 ,  G11C11/24

CPC分类号： G11C11/4072

摘要： A dynamic semiconductor memory device includes data output lines (D, D), a data output buffer (12), a column enable buffer (9), and an output enable buffer (11) for generating an output enable signal (OE) to enable the transmission of data from the data output lines to the data buffer. The output enable buffer is driven by the clock signals of the column enable buffer. An output disabling circuit (13) is provided to stop the generation of an output enable signal by the output enable buffer when the output enable buffer is not being driven by the column enable buffer. As a result, the data output buffer assumes a high-impedance state when a power supply is turned on.

摘要翻译： 动态半导体存储器件包括数据输出线（D，＆amp; upbar＆D），数据输出缓冲器（12），列使能缓冲器（9）和用于产生输出使能信号（OE）的输出使能信号 使数据从数据输出线传输到数据缓冲区。 输出使能缓冲器由列使能缓冲器的时钟信号驱动。 提供输出禁止电路（13），用于当输出使能缓冲器不被列使能缓冲器驱动时，通过输出使能缓冲器停止产生输出使能信号。 结果，当电源接通时，数据输出缓冲器呈现高阻抗状态。

公开(公告)号：US4742486A

公开(公告)日：1988-05-03

申请号：US861199

申请日：1986-05-08

申请人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Masao Nakano ,  Kimiaki Sato ,  Nobumi Kodama

发明人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Masao Nakano ,  Kimiaki Sato ,  Nobumi Kodama

IPC分类号： G06F11/22 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/267 ,  G11C11/34 ,  G11C11/401 ,  G11C17/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C13/00

CPC分类号： G01R31/31701 ,  G11C29/46 ,  G06F11/267

摘要： In a semiconductor integrated circuit comprising an internal circuit, a device for receiving a chip select signal from the outside, a device for receiving an input signal from the outside, and a voltage detecting circuit for detecting whether or not the potential of the input signal is higher than a reference potential; the voltage detecting circuit comprises a first device for differentially comparing the potential of the input signal with the reference potential and generating an output potential in accordance with the results of the comparison, a second device for detecting a predetermined edge of the chip select signal so as to trigger the first device, and a third device for latching the output potential of the first device to the third device when the first device is triggered by the second device, the internal circuit being switched from a first mode to a second mode, or vice versa, in accordance with the output potential of the third device.

摘要翻译： 在包括内部电路的半导体集成电路中，用于从外部接收芯片选择信号的装置，用于从外部接收输入信号的装置以及检测输入信号的电位是否为 高于参考电位; 所述电压检测电路包括用于将所述输入信号的电位与所述参考电位进行差分比较并根据所述比较结果产生输出电位的第一装置，用于检测所述芯片选择信号的预定边沿的第二装置，以便 触发第一装置，以及第三装置，用于当第一装置被第二装置触发时将第一装置的输出电位锁定到第三装置，内部电路从第一模式切换到第二模式，或者副 反之亦然，根据第三器件的输出电位。

公开(公告)号：US4716549A

公开(公告)日：1987-12-29

申请号：US901680

申请日：1986-08-29

申请人： Masao Nakano ,  Yoshihiro Takemae ,  Tomio Nakano ,  Shigeki Nozaki ,  Kimiaki Sato ,  Nobumi Kodama

发明人： Masao Nakano ,  Yoshihiro Takemae ,  Tomio Nakano ,  Shigeki Nozaki ,  Kimiaki Sato ,  Nobumi Kodama

IPC分类号： G11C11/407 ,  G11C11/40 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4099 ,  G11C7/02 ,  G11C11/24

CPC分类号： G11C11/4099 ,  G11C11/4094

摘要： A semiconductor memory device capable of compensating for variation in a discriminating voltage of a memory cell comprising a memory cell and a gate circuit for coupling the memory cell to a bit line. The device has a precharge circuit for precharging the bit line pair to a predetermined resultant precharge voltage in a reset state. The precharge circuit precharges a bit line pair with the resultant precharge voltage obtained by adding a compensating voltage to a precharge voltage in the reset state. The compensating voltage is adapted to compensate for variation in a memory cell discriminating voltage based on variation in a memory cell voltage caused by capacitive coupling of a word line to a memory capacitor due to a parasitic capacitance of a gate circuit in the active state, and the precharge voltage is adapted to optimize the memory cell discriminating voltage when it is assumed that the parasitic capacitance is not present.

摘要翻译： 一种半导体存储器件，其能够补偿包括存储单元的存储单元和用于将存储单元耦合到位线的门电路的识别电压的变化。 该装置具有用于在复位状态下将位线对预充电到预定的合成预充电电压的预充电电路。 预充电电路对通过在复位状态下将补偿电压加到预充电电压而获得的所得预充电电压对位线对进行预充电。 补偿电压适于基于由于处于活动状态的栅极电路的寄生电容而由字线与存储电容器的电容耦合而引起的存储单元电压的变化来补偿存储单元识别电压的变化，以及 当假设寄生电容不存在时，预充电电压适于优化存储单元识别电压。

公开(公告)号：US4387448A

公开(公告)日：1983-06-07

申请号：US254541

申请日：1981-04-15

申请人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsutomu Mezawa

发明人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsutomu Mezawa

IPC分类号： G11C11/409 ,  G11C7/12 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C11/4094 ,  G11C7/12

摘要： Disclosed is a dynamic semiconductor memory device with decreased clocks having a pull up circuit associated with a pair of bit lines. The pull up circuit comprises a pair of first switching transistors connected between a power supply line and the associated bit line, and, a pair of second switching transistors. Each gate of the second switching transistors is connected to the bit line of opposite side. The turning on or off of the second switching transistor controls the gate potential of the first switching transistor.

摘要翻译： 公开了一种具有降低的时钟的动态半导体存储器件，其具有与一对位线相关联的上拉电路。 上拉电路包括连接在电源线和相关联的位线之间的一对第一开关晶体管和一对第二开关晶体管。 第二开关晶体管的每个栅极连接到相对侧的位线。 第二开关晶体管的导通或截止控制第一开关晶体管的栅极电位。