公开(公告)号：US20070052082A1

公开(公告)日：2007-03-08

申请号：US11306818

申请日：2006-01-12

申请人： Cheng-Yin Lee ,  Chih-Ming Chung ,  Wen-Pin Huang

发明人： Cheng-Yin Lee ,  Chih-Ming Chung ,  Wen-Pin Huang

IPC分类号： H01L23/02

CPC分类号： H01L25/03 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00

摘要： A multi-chip package structure including a carrier, a first chip having an active surface and a rear surface, multiple bumps, a second chip, multiple first bonding wires, a package unit disposed above the first chip, a spacer disposed between the package unit and the first chip, multiple second bonding wires, and an encapsulant is provided. The bumps are disposed between the active surface and the carrier to electrically connect the first chip and the carrier. The second chip is disposed on the rear surface of the first chip. The first bonding wires electrically connect the second chip and the carrier. The second bonding wires electrically connect the package unit and the carrier. The encapsulant is disposed on the carrier to encapsulate the first chip, the second chip, at least a portion of the package unit, the bumps, the spacer, the first bonding wires and the second bonding wires.

摘要翻译： 一种包括载体，具有活性表面的第一芯片和后表面的多芯片封装结构，多个凸点，第二芯片，多个第一接合线，设置在第一芯片上方的封装单元，设置在封装单元之间的间隔件 并提供第一芯片，多个第二接合线和密封剂。 凸起设置在有源表面和载体之间以电连接第一芯片和载体。 第二芯片设置在第一芯片的后表面上。 第一接合线将第二芯片和载体电连接。 第二接合线将封装单元和载体电连接。 密封剂设置在载体上以封装第一芯片，第二芯片，封装单元的至少一部分，凸块，间隔件，第一接合线和第二接合线。

公开(公告)号：US20050082656A1

公开(公告)日：2005-04-21

申请号：US10934409

申请日：2004-09-07

申请人： Chi Chu ,  Cheng-Yin Lee ,  Gwo-Liang Weng ,  Shih-Chang Lee

发明人： Chi Chu ,  Cheng-Yin Lee ,  Gwo-Liang Weng ,  Shih-Chang Lee

IPC分类号： H01L25/065 ,  H01L23/02

CPC分类号： H01L25/0657 ,  H01L2224/16145 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/18161

摘要： A Stackable package module comprises a plurality of semiconductor devices in stack. One of the semiconductor devices includes a chip with an active surface and a corresponding back surface, a plurality of solder bumps and a plurality of stud bumps. The solder bumps are formed on the active surface. The stud bumps are formed on the back surface. Each stud bump has a bump body and a protruding trail by wire-bonding and cutting. Bumps of another package are bonded on the stub bumps for replacing known intermediate substrate in conventional stacked package module.

摘要翻译： 可堆叠封装模块包括堆叠中的多个半导体器件。 半导体器件中的一个包括具有活性表面和对应的背面的芯片，多个焊料凸块和多个凸块凸块。 焊料凸块形成在有源表面上。 柱形凸块形成在背面。 每个柱形凸起具有凸起体和通过引线接合和切割的突出轨迹。 另一个封装的凸块被结合在短截线凸起上，用于替代传统堆叠封装模块中的已知中间衬底。

公开(公告)号：US07442580B2

公开(公告)日：2008-10-28

申请号：US11637786

申请日：2006-12-13

申请人： Gwo-Liang Weng ,  Cheng-Yin Lee

发明人： Gwo-Liang Weng ,  Cheng-Yin Lee

IPC分类号： H01L21/00

CPC分类号： H01L21/561 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/97 ,  H01L27/14618 ,  H01L31/0203 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A manufacturing method of a package structure is provided. Firstly, a substrate having a surface is provided. Next, a chip is disposed on the surface of the substrate. Then, a packing material layer is formed on the surface of the substrate. Next, a this film is pasted on the packing material layer. Then the substrate and the packing material layer are thoroughly cut along a cutting line around the chip by a first cutting blade but the thin film is not cut thoroughly. Next, the substrate is thoroughly cut along at least a part of the cutting line by a second cutting blade but the packing material layer is not thoroughly cut such that a part of the packing material layer is exposed. The width of the second cutting blade is larger than the width of the first cutting blade.

摘要翻译： 提供一种封装结构的制造方法。 首先，提供具有表面的基板。 接下来，将芯片设置在基板的表面上。 然后，在基板的表面上形成包装材料层。 接下来，将该膜粘贴在包装材料层上。 然后，通过第一切割刀沿着芯片周围的切割线彻底切割基板和包装​​材料层，但是薄膜未被彻底切割。 接下来，通过第二切割刀沿着切割线的至少一部分彻底切割基板，但是包装材料层未被彻底切割，使得包装材料层的一部分露出。 第二切割刀片的宽度大于第一切割刀片的宽度。

公开(公告)号：US20080076208A1

公开(公告)日：2008-03-27

申请号：US11828352

申请日：2007-07-26

申请人： Yen-Yi Wu ,  Wei-Yueh Sung ,  Pao-Huei Chang Chien ,  Chi-Chih Chu ,  Cheng-Yin Lee ,  Gwo-Liang Weng

发明人： Yen-Yi Wu ,  Wei-Yueh Sung ,  Pao-Huei Chang Chien ,  Chi-Chih Chu ,  Cheng-Yin Lee ,  Gwo-Liang Weng

IPC分类号： H01L21/00

CPC分类号： H01L24/14 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/1405 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.

摘要翻译： 本发明涉及半导体封装和半导体器件及其制造方法。 制造半导体封装的方法包括：提供衬底; 将芯片附接到所述基板的表面; 形成用于电连接所述芯片和所述基板的多个连接元件; 在所述基板的表面上形成多个第一导电体; 形成用于封装基板，芯片，连接元件和第一导电体的表面的模塑料; 并且除去模塑料的边界部分的一部分，使得模塑料具有两个高度，并且暴露出每个第一导电体的一端。 因此，成型化合物覆盖基板的整个表面，使得基板表面上的接合焊盘不会被污染。

公开(公告)号：US20070224732A1

公开(公告)日：2007-09-27

申请号：US11637786

申请日：2006-12-13

申请人： Gwo-Liang Weng ,  Cheng-Yin Lee

发明人： Gwo-Liang Weng ,  Cheng-Yin Lee

IPC分类号： H01L21/00

CPC分类号： H01L21/561 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/97 ,  H01L27/14618 ,  H01L31/0203 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A manufacturing method of a package structure is provided. Firstly, a substrate having a surface is provided. Next, a chip is disposed on the surface of the substrate. Then, a packing material layer is formed on the surface of the substrate. Next, a thin film is pasted on the packing material layer. Then, the substrate and the packing material layer are thoroughly cut along a cutting line around the chip by a first cutting blade but the thin film is not cut thoroughly. Next, the substrate is thoroughly cut along at least a part of the cutting line by a second cutting blade but the packing material layer is not thoroughly cut such that a part of the packing material layer is exposed. The width of the second cutting blade is larger than the width of the first cutting blade.

摘要翻译： 提供一种封装结构的制造方法。 首先，提供具有表面的基板。 接下来，将芯片设置在基板的表面上。 然后，在基板的表面上形成包装材料层。 接着，将薄膜贴在包装材料层上。 然后，通过第一切割刀沿着芯片周围的切割线彻底切割基板和包装​​材料层，但是薄膜未被彻底切割。 接下来，通过第二切割刀沿着切割线的至少一部分彻底切割基板，但是包装材料层未被彻底切割，使得包装材料层的一部分露出。 第二切割刀片的宽度大于第一切割刀片的宽度。

公开(公告)号：US07061079B2

公开(公告)日：2006-06-13

申请号：US10904574

申请日：2004-11-17

申请人： Gwo-Liang Weng ,  Shih-Chang Lee ,  Cheng-Yin Lee

发明人： Gwo-Liang Weng ,  Shih-Chang Lee ,  Cheng-Yin Lee

IPC分类号： H01L23/495

CPC分类号： H01L23/49517 ,  H01L23/3107 ,  H01L23/4334 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2225/1029 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a chip package structure and the manufacturing method thereof, which affords higher heat dissipation efficiency and is suitable to fabricate the stack type package structure with a higher integration. The chip package structure comprises a carrier, at least a chip, a heat sink and a mold compound. The chip is disposed on the carrier, while the bonding pads of the chip are electrically connected to the leads of the carrier. The heat sink is disposed over the chip and includes at least a body and a plurality of connecting portions. The connecting portions are disposed around a periphery of the body and are electrically connected to the leads. By using a specially designed heat sink, the chip package structure can afford better heat dissipation and be suitable to form stack type package structures.

摘要翻译： 本发明提供了一种芯片封装结构及其制造方法，其提供较高的散热效率，并且适于制造具有更高集成度的堆叠型封装结构。 芯片封装结构包括载体，至少芯片，散热器和模具化合物。 芯片设置在载体上，而芯片的焊盘电连接到载体的引线。 散热器设置在芯片上方并且包括至少一个主体和多个连接部分。 连接部分围绕主体的周边设置并且电连接到引线。 通过使用专门设计的散热器，芯片封装结构可以提供更好的散热性能，适合形成堆叠式封装结构。

公开(公告)号：US20050181543A1

公开(公告)日：2005-08-18

申请号：US10907561

申请日：2005-04-06

申请人： Shih-Chang Lee ,  Gwo-Liang Weng ,  Wei-Chang Tai ,  Cheng-Yin Lee

发明人： Shih-Chang Lee ,  Gwo-Liang Weng ,  Wei-Chang Tai ,  Cheng-Yin Lee

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L25/10 ,  H05K1/18 ,  H05K3/28 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/48

CPC分类号： H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0655 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/181 ,  H05K3/284 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A process for fabricating a multi-chip package module is disclosed. A substrate, at least a first chip and at least a second chip are provided. The backside of the first chip is attached to a die pad on a substrate. A wire-bonding operation is carried out to electrically connect the first chip and the substrate through conductive wires. A plurality of bumps is bonded to the second chip so that one end of each bump is bonded to a contact on the second chip. Thereafter, the other end of each bump is bonded to a contact on the substrate so that the second chip and the substrate are physically and electrically connected together. Finally, an encapsulation process is performed to form a packaging material enclosing the first chip, the second chip, the conductive wires, the bumps and the substrate.

摘要翻译： 公开了一种用于制造多芯片封装模块的工艺。 提供基板，至少第一芯片和至少第二芯片。 第一芯片的背面连接到基板上的芯片焊盘。 进行引线接合操作，以通过导线将第一芯片和基板电连接。 将多个凸块接合到第二芯片，使得每个凸块的一端接合到第二芯片上的触点。 此后，每个凸块的另一端结合到基板上的接触件，使得第二芯片和基板物理和电连接在一起。 最后，进行包封处理以形成封装第一芯片，第二芯片，导线，凸块和基板的封装材料。

公开(公告)号：US06879594B1

公开(公告)日：2005-04-12

申请号：US09588533

申请日：2000-06-07

申请人： Cheng-Yin Lee ,  Loa Andersson

发明人： Cheng-Yin Lee ,  Loa Andersson

IPC分类号： H04L12/18 ,  H04L12/56 ,  H04L12/28

CPC分类号： H04L45/18 ,  H04L12/185 ,  H04L45/02 ,  H04L45/16 ,  H04L45/50

摘要： A method for avoiding loops from forming when setting up label switched paths is provided. The method uses a Label Splicing Message is followed by an Acknowledgment message to determine if loops are formed in the process of joining a new node or subtree to a multicast MPLS tree. By verifying that the path towards the root of the MPLS tree is loop-free during the construction of the tree, this method complements the loop detection mechanism provided by the label switched protocol (LDP).

摘要翻译： 提供了一种在设置标签交换路径时避免形成环路的方法。 该方法使用标签拼接消息后跟一个确认消息，以确定在将新节点或子树加入组播MPLS树的过程中是否形成循环。 通过验证在树的构建过程中到达树根的路径是无环路的，该方法补充了标签交换协议（LDP）提供的环路检测机制。

公开(公告)号：US07619966B2

公开(公告)日：2009-11-17

申请号：US10724775

申请日：2003-12-02

申请人： Cheng-Yin Lee

发明人： Cheng-Yin Lee

IPC分类号： G01R31/08

CPC分类号： H04L12/4641 ,  H04L12/462 ,  H04L12/4625 ,  H04L12/4645 ,  H04L45/02 ,  H04L45/22 ,  H04L45/28 ,  H04L45/68 ,  H04L47/10 ,  H04L47/20

摘要： This invention is applicable to a Virtual Private LAN service built using multiple point-to-point Ethernet services from a network operator, where the bridging and the transport/tunneling of Ethernet frames to a remote site are decoupled. The learning bridge function (including MAC address learning and flooding) is performed at customer equipment CE devices, while the tunneling is performed at provider edge PE nodes. The models described here for this VPN refer to hub redundancy, site-to-site SLA guarantees and address discovery in the case of hybrid connections.

摘要翻译： 本发明适用于使用来自网络运营商的多点对点以太网服务构建的虚拟专用LAN服务，其中以太网帧到远程站点的桥接和传输/隧道被去耦合。 在客户设备CE设备上执行学习桥功能（包括MAC地址学习和泛洪），同时在提供商边缘PE节点执行隧道。 这里描述的这个VPN模型指的是混合连接情况下的集线器冗余，站点到站点SLA保证和地址发现。

公开(公告)号：US07473629B2

公开(公告)日：2009-01-06

申请号：US11634059

申请日：2006-12-06

申请人： Wei-Chang Tai ,  Chi-Chih Chu ,  Meng-Jung Chuang ,  Cheng-Yin Lee ,  Yao-Ting Huang ,  Kuang-Lin Lo

发明人： Wei-Chang Tai ,  Chi-Chih Chu ,  Meng-Jung Chuang ,  Cheng-Yin Lee ,  Yao-Ting Huang ,  Kuang-Lin Lo

IPC分类号： H01L21/44

CPC分类号： H05K3/3452 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H05K3/284 ,  H05K2203/0588 ,  H01L2924/00014 ,  H01L2924/00

摘要： A substrate structure having a solder mask and a process for making the same, including (a) providing a substrate having a top surface, the top surface having a die pad and a plurality of solder pads; (b) forming a first solder mask on the top surface, the first solder mask having a plurality of openings, each opening corresponding to each solder pad so as to expose at least part of the solder pad; and (c) forming a second solder mask on the first solder mask. The substrate structure can be used for packaging a thicker die so as to prevent the die crack and the overflow of molding compound will be avoided.

摘要翻译： 一种具有焊料掩模的衬底结构及其制造方法，包括：（a）提供具有顶表面的衬底，所述顶表面具有管芯焊盘和多个焊盘; （b）在所述顶表面上形成第一焊料掩模，所述第一焊料掩模具有多个开口，每个开口对应于每个焊盘，以暴露所述焊盘的至少一部分; 和（c）在第一焊料掩模上形成第二焊料掩模。 衬底结构可用于包装较厚的模具，以防止模具裂纹，并避免模塑料的溢流。