公开(公告)号：US20090269911A1

公开(公告)日：2009-10-29

申请号：US12484273

申请日：2009-06-15

申请人： Kiyoshi KATO ,  Yoshiyuki KUROKAWA

发明人： Kiyoshi KATO ,  Yoshiyuki KUROKAWA

IPC分类号： H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/7881

摘要： A non-volatile memory in which a leak current from an electric charge accumulating layer to an active layer is reduced and a method of manufacturing the non-volatile memory are provided. In a non-volatile memory made from a semiconductor thin film that is formed on a substrate (101) having an insulating surface, active layer side ends (110) are tapered. This makes the thickness of a first insulating film (106), which is formed by a thermal oxidization process, at the active layer side ends (110) the same as the thickness of the rest of the first insulating film. Therefore local thinning of the first insulating film does not take place. Moreover, the tapered active layer side ends hardly tolerate electric field concentration at active layer side end corners (111). Accordingly, a leak current from an electric charge accumulating layer (107) to the active layer (105) is reduced to improve the electric charge holding characteristic. As a result, the first insulating film can be further made thin to obtain a high performance non-volatile memory that operates at a low voltage and consumes less power.

摘要翻译： 提供了从电荷累积层到有源层的泄漏电流减小的非易失性存储器以及制造非易失性存储器的方法。 在由形成在具有绝缘表面的基板（101）上的由半导体薄膜制成的非易失性存储器中，有源层侧端（110）是锥形的。 这使得通过热氧化工艺形成的第一绝缘膜（106）在有源层侧端部（110）的厚度与第一绝缘膜的其余部分的厚度相同。 因此，不会发生第一绝缘膜的局部变薄。 此外，锥形有源层侧端部难以容忍有源层侧端角处的电场浓度（111）。 因此，减少了从电荷累积层（107）到有源层（105）的泄漏电流，以改善电荷保持特性。 结果，可以进一步使第一绝缘膜变薄，以获得在低电压下工作并消耗更少功率的高性能非易失性存储器。

公开(公告)号：US20120139872A1

公开(公告)日：2012-06-07

申请号：US13367634

申请日：2012-02-07

申请人： Kiyoshi KATO ,  Toshihiko SAITO

发明人： Kiyoshi KATO ,  Toshihiko SAITO

IPC分类号： G09G3/36 ,  G06F3/045

CPC分类号： G02F1/13338 ,  G02F1/13306 ,  G02F1/133305 ,  G02F1/133345 ,  G02F1/13439 ,  G02F1/13454 ,  G02F1/136213 ,  G02F1/1368 ,  G02F2201/123 ,  G06F3/0412 ,  G06F3/044 ,  G09G3/36 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288 ,  H01L27/13 ,  H01L27/3244 ,  H01L29/78621 ,  H01L29/78645

摘要： A variable capacitor is formed from a pair of electrodes and a dielectric interposed between the electrodes over a substrate, and an external input is detected by changing capacitance of the variable capacitor by a physical or electrical force. Specifically, a variable capacitor and a sense amplifier are provided over the same substrate, and the sense amplifier reads the change of capacitance of the variable capacitor and transmits a signal in accordance with the input to a control circuit.

摘要翻译： 可变电容器由一对电极和位于基板之间的电极之间的电介质形成，并且通过用物理或电力改变可变电容器的电容来检测外部输入。 具体地说，在同一衬底上设置可变电容器和读出放大器，读出放大器读取可变电容器的电容变化，并根据输入将信号发送到控制电路。

公开(公告)号：US20120074481A1

公开(公告)日：2012-03-29

申请号：US13314280

申请日：2011-12-08

申请人： Shunpei YAMAZAKI ,  Kiyoshi KATO

发明人： Shunpei YAMAZAKI ,  Kiyoshi KATO

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L23/49855 ,  G06K19/07749 ,  G06K19/07758 ,  G06K19/07767 ,  G07D7/01 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides an ID chip with reduced cost, increased impact resistance and attractive design, as well as products and the like mounting the ID chip and a manufacturing method thereof. In view of the foregoing, an integrated circuit having a semiconductor film with a thickness of 0.2 μm or less is mounted on securities including bills, belongings, containers of food and drink, and the like (hereinafter referred to as products and the like). The ID chip of the invention can be reduced in cost and increased in impact resistance as compared with a chip formed over a silicon wafer while maintaining an attractive design.

摘要翻译： 本发明提供一种具有降低成本，增加耐冲击性和有吸引力的设计的ID芯片以及安装ID芯片的产品等及其制造方法。 鉴于上述，将厚度为0.2μm以下的半导体膜的集成电路安装在包括纸币，财物，食品和饮料容器等的证券（以下称为产品等）上。 与保持有吸引力的设计的硅晶片上形成的芯片相比，本发明的ID芯片可以降低成本并增加耐冲击性。

公开(公告)号：US20110255325A1

公开(公告)日：2011-10-20

申请号：US13082464

申请日：2011-04-08

申请人： Shuhei NAGATSUKA ,  Kiyoshi KATO ,  Takanori MATSUZAKI ,  Hiroki INOUE

发明人： Shuhei NAGATSUKA ,  Kiyoshi KATO ,  Takanori MATSUZAKI ,  Hiroki INOUE

IPC分类号： G11C5/06

CPC分类号： G11C11/4093 ,  G11C11/405 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4096 ,  H01L27/1156 ,  H01L27/1203

摘要： An object is to provide a semiconductor device having a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device includes a memory cell including a widegap semiconductor, for example, an oxide semiconductor. The memory cell includes a writing transistor, a reading transistor, and a selecting transistor. Using a widegap semiconductor, a semiconductor device capable of sufficiently reducing the off-state current of a transistor included in a memory cell and holding data for a long time can be provided.

摘要翻译： 目的是提供一种具有新颖结构的半导体器件，其即使在未被供电且具有无限数量的写周期的情况下也能够保存存储的数据。 半导体器件包括具有宽栅半导体的存储单元，例如氧化物半导体。 存储单元包括写入晶体管，读取晶体管和选择晶体管。 使用宽栅半导体，可以提供能够充分降低存储单元中包含的晶体管的截止电流并长时间保持数据的半导体器件。

公开(公告)号：US20110227074A1

公开(公告)日：2011-09-22

申请号：US13045873

申请日：2011-03-11

申请人： Kiyoshi KATO ,  Shuhei NAGATSUKA

发明人： Kiyoshi KATO ,  Shuhei NAGATSUKA

IPC分类号： H01L27/088

CPC分类号： H01L27/1108 ,  G11C16/0408 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60

摘要： A semiconductor device with a novel structure is provided in which stored data can be held even when power is not supplied and the number of writing is not limited. The semiconductor includes a second transistor and a capacitor over a first transistor. The capacitor includes a source or drain electrode and a gate insulating layer of the second transistor and a capacitor electrode over an insulating layer which covers the second transistor. The gate electrode of the second transistor and the capacitor electrode overlap at least partly with each other with the insulating layer interposed therebetween. By forming the gate electrode of the second transistor and the capacitor electrode using different layers, an integration degree of the semiconductor device can be improved.

摘要翻译： 提供具有新颖结构的半导体器件，其中即使在不提供电力并且写入次数不受限制的情况下，也可以保持存储的数据。 半导体在第一晶体管上包括第二晶体管和电容器。 电容器包括源极或漏极以及第二晶体管的栅极绝缘层，以及覆盖第二晶体管的绝缘层上的电容器电极。 第二晶体管的栅电极和电容器电极至少部分地彼此重叠，绝缘层位于它们之间。 通过使用不同层来形成第二晶体管的栅电极和电容电极，可以提高半导体器件的集成度。

公开(公告)号：US20110114941A1

公开(公告)日：2011-05-19

申请号：US12943532

申请日：2010-11-10

申请人： Kiyoshi KATO ,  Yoshinori IEDA ,  Jun KOYAMA

发明人： Kiyoshi KATO ,  Yoshinori IEDA ,  Jun KOYAMA

IPC分类号： H01L29/786

CPC分类号： H01L27/12 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/77 ,  H01L27/11521 ,  H01L27/1225 ,  H01L29/42324 ,  H01L29/7881

摘要： A device including a novel nonvolatile memory element is provided. A device including a nonvolatile memory element in which an oxide semiconductor is used as a semiconductor material for a channel formation region. The nonvolatile memory element includes a control gate, a charge accumulation layer which overlaps with the control gate with a first insulating film provided therebetween, and an oxide semiconductor layer formed using an oxide semiconductor material, which overlaps with the charge accumulation layer with a second insulating film provided therebetween.

摘要翻译： 提供了包括新颖的非易失性存储元件的装置。 包括其中使用氧化物半导体作为沟道形成区域的半导体材料的非易失性存储元件的器件。 非易失性存储元件包括控制栅极，与控制栅极重叠的电荷累积层，其间设置有第一绝缘膜，以及使用氧化物半导体材料形成的氧化物半导体层，其与电荷累积层重叠，具有第二绝缘 膜之间。

公开(公告)号：US20110089475A1

公开(公告)日：2011-04-21

申请号：US12977836

申请日：2010-12-23

申请人： Hajime TOKUNAGA ,  Kiyoshi KATO

发明人： Hajime TOKUNAGA ,  Kiyoshi KATO

IPC分类号： H01L27/108

CPC分类号： H01L27/13

摘要： A memory device capable of data writing at a time other than during manufacturing is provided by using a memory element including an organic material. In a memory cell, a third conductive film, an organic compound, and a fourth conductive film are stacked over a semiconductor film provided with an n-type impurity region and a p-type impurity region, and a pn-junction diode is serially connected to the memory element. A logic circuit for controlling the memory cell includes a thin film transistor. The memory cell and the logic circuit are manufactured over one substrate at the same time. The n-type impurity region and the p-type impurity region of the memory cell are manufactured at the same time as the impurity region of the thin film transistor.

摘要翻译： 通过使用包括有机材料的存储元件，能够在除制造之外的时间进行数据写入的存储器件。 在存储单元中，在设置有n型杂质区域和p型杂质区域的半导体膜上堆叠第三导电膜，有机化合物和第四导电膜，并且pn结二极管串联连接 到存储元件。 用于控制存储单元的逻辑电路包括薄膜晶体管。 存储单元和逻辑电路同时在一个衬底上制造。 与薄膜晶体管的杂质区域同时制造存储单元的n型杂质区域和p型杂质区域。

公开(公告)号：US20110049522A1

公开(公告)日：2011-03-03

申请号：US12711611

申请日：2010-02-24

申请人： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Masahiko HAYAKAWA ,  Kiyoshi KATO ,  Mitsuaki OSAME

发明人： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Masahiko HAYAKAWA ,  Kiyoshi KATO ,  Mitsuaki OSAME

IPC分类号： H01L33/00

CPC分类号： H01L27/1248 ,  G02F1/136227 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1255 ,  H01L27/13 ,  H01L27/3246 ,  H01L27/3276 ,  H01L33/52 ,  H01L51/5237 ,  H01L51/5253

摘要： It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film. Then, in the opening part of the organic resin film, a gate insulating film and the two layer inorganic insulating film containing nitrogen are opened partially is by etching to expose an active layer of the TFT.

摘要翻译： 本发明的目的是提供一种具有层间绝缘膜的半导体显示装置，其可以在控制成膜时间的同时获得表面的平面性，并且可以控制用于除去水分的加热处理的处理时间，并且可以防止水分 在层间绝缘膜中不被放电到与层间绝缘膜相邻的膜或电极。 形成与有机树脂相比不容易透过水分的含氮的无机绝缘膜，以覆盖TFT。 接着，在有机绝缘膜上涂布含有感光性丙烯酸树脂的有机树脂膜，将有机树脂膜部分地曝光以打开。 然后，形成与有机树脂相比不容易透过水分的含有氮的无机绝缘膜，以覆盖打开的有机树脂膜。 然后，在有机树脂膜的开口部分，通过蚀刻部分地开启含有氮的栅极绝缘膜和双层无机绝缘膜，以暴露TFT的有源层。

公开(公告)号：US20100148845A1

公开(公告)日：2010-06-17

申请号：US12713723

申请日：2010-02-26

申请人： Kiyoshi KATO

发明人： Kiyoshi KATO

IPC分类号： H03L5/00

CPC分类号： H01L27/1266 ,  G06K19/07735 ,  G06K19/07749 ,  H01L23/49855 ,  H01L27/0266 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/13 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  H01L2924/00

摘要： The limiter of the invention uses as a diode a stacked gate thin film transistor (TFT) including a floating gate. When the TFT including a floating gate is used, the threshold voltage Vth may be corrected by controlling the amount of charge accumulated in the floating gate even in the case where there are variations in the threshold voltages Vth of the TFT.

摘要翻译： 本发明的限幅器使用包括浮动栅极的堆叠栅极薄膜晶体管（TFT）作为二极管。 当使用包括浮置栅极的TFT时，即使在TFT的阈值电压Vth发生变化的情况下，也可以通过控制浮置栅极中累积的电荷量来校正阈值电压Vth。

公开(公告)号：US20080273357A1

公开(公告)日：2008-11-06

申请号：US11957560

申请日：2007-12-17

申请人： Chikako MATSUMOTO ,  Kiyoshi KATO

发明人： Chikako MATSUMOTO ,  Kiyoshi KATO

IPC分类号： H02M3/18

CPC分类号： H02M3/073

摘要： To provide a semiconductor device of which a manufacturing process is simplified and which has a boosting circuit in which the area of a capacitor element is reduced. The present invention includes a plurality of rectifying elements which is connected in series and has a rectifying function from a first input terminal portion to an output terminal portion; a first wiring and a second wiring, which are connected to a second input terminal portion, into which a signal and a signal obtained by inverting the signal are respectively input; and a boosting circuit including a plurality of capacitor elements each having a first electrode, an insulating film, and a second electrode and storing a boosted potential. The plurality of capacitor elements includes a capacitor element in which the first electrode and the second electrode are formed using conductive films, and a capacitor element in which at least the second electrode is formed using a semiconductor film. In the plurality of capacitor elements, at least a capacitor element in a first stage is a capacitor element in which the first electrode and the second electrode are formed using conductive films.

摘要翻译： 为了提供其制造工艺简化的半导体器件，并且具有其中电容器元件的面积减小的升压电路。 本发明包括串联连接并具有从第一输入端子部分到输出端子部分的整流功能的多个整流元件; 第一布线和第二布线，其连接到第二输入端子部分，分别输入信号和通过反相信号获得的信号; 以及包括多个电容器元件的升压电路，每个电容器元件具有第一电极，绝缘膜和第二电极，并且存储升压电位。 多个电容器元件包括其中使用导电膜形成第一电极和第二电极的电容器元件，以及至少使用半导体膜形成第二电极的电容器元件。 在多个电容器元件中，第一级中的至少一个电容器元件是使用导电膜形成第一电极和第二电极的电容器元件。