公开(公告)号：US20090269911A1

公开(公告)日：2009-10-29

申请号：US12484273

申请日：2009-06-15

申请人： Kiyoshi KATO ,  Yoshiyuki KUROKAWA

发明人： Kiyoshi KATO ,  Yoshiyuki KUROKAWA

IPC分类号： H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/7881

摘要： A non-volatile memory in which a leak current from an electric charge accumulating layer to an active layer is reduced and a method of manufacturing the non-volatile memory are provided. In a non-volatile memory made from a semiconductor thin film that is formed on a substrate (101) having an insulating surface, active layer side ends (110) are tapered. This makes the thickness of a first insulating film (106), which is formed by a thermal oxidization process, at the active layer side ends (110) the same as the thickness of the rest of the first insulating film. Therefore local thinning of the first insulating film does not take place. Moreover, the tapered active layer side ends hardly tolerate electric field concentration at active layer side end corners (111). Accordingly, a leak current from an electric charge accumulating layer (107) to the active layer (105) is reduced to improve the electric charge holding characteristic. As a result, the first insulating film can be further made thin to obtain a high performance non-volatile memory that operates at a low voltage and consumes less power.

摘要翻译： 提供了从电荷累积层到有源层的泄漏电流减小的非易失性存储器以及制造非易失性存储器的方法。 在由形成在具有绝缘表面的基板（101）上的由半导体薄膜制成的非易失性存储器中，有源层侧端（110）是锥形的。 这使得通过热氧化工艺形成的第一绝缘膜（106）在有源层侧端部（110）的厚度与第一绝缘膜的其余部分的厚度相同。 因此，不会发生第一绝缘膜的局部变薄。 此外，锥形有源层侧端部难以容忍有源层侧端角处的电场浓度（111）。 因此，减少了从电荷累积层（107）到有源层（105）的泄漏电流，以改善电荷保持特性。 结果，可以进一步使第一绝缘膜变薄，以获得在低电压下工作并消耗更少功率的高性能非易失性存储器。

公开(公告)号：US20120192014A1

公开(公告)日：2012-07-26

申请号：US13433886

申请日：2012-03-29

申请人： Kiyoshi KATO

发明人： Kiyoshi KATO

IPC分类号： G06F11/30

CPC分类号： G06F11/3447 ,  G06F11/3409 ,  G06F2201/81

摘要： An operations management apparatus which acquires performance information for each of a plurality of performance items from a plurality of controlled units and manages operation of the controlled units includes a correlation model generation unit which derives a correlation function between a first series of performance information that indicates time series variation about a first element and a second series of performance information that indicates time series variation about a second element, generates a correlation model between the first element and the second element based on the correlation function, and obtains the correlation model for each element pair of the performance information, and a correlation change analysis unit which analyzes a change in the correlation model based on the performance information acquired newly which has not been used for generation of the correlation model.

摘要翻译： 一种操作管理装置，其从多个受控单位取得多个演奏项目的演奏信息，并管理被控制的单位的动作，包括：相关模型生成部，其将表示时刻的第一系列演奏信息， 关于第一元素的系列变化和指示关于第二元素的时间序列变化的第二系列性能信息，基于相关函数在第一元素和第二元素之间生成相关模型，并获得每个元素对的相关模型 以及相关变化分析单元，其基于未被用于生成相关模型的新获得的性能信息来分析相关模型的变化。

公开(公告)号：US20120043388A1

公开(公告)日：2012-02-23

申请号：US13287569

申请日：2011-11-02

申请人： Toshihiko SAITO ,  Yutaka SHIONOIRI ,  Kiyoshi KATO

发明人： Toshihiko SAITO ,  Yutaka SHIONOIRI ,  Kiyoshi KATO

IPC分类号： G06K19/06

CPC分类号： H01L27/12 ,  G06K19/0701 ,  G06K19/0715 ,  G06K19/0723 ,  H01L21/84

摘要： An object of the present invention is to provide a semiconductor device which can obtain the high potential necessary for writing data to a memory, using a small circuit area. In the present invention, by using as input voltage of a booster circuit not the conventionally used output VDD of a regulator circuit 104, but rather an output VDD0 of a rectifier circuit portion 103, which is a higher potential than the VDD, the high potential necessary for writing data to a memory can be obtained with a small circuit area.

摘要翻译： 本发明的目的是提供一种使用小电路区域可以获得将数据写入存储器所需的高电位的半导体器件。 在本发明中，通过使用升压电路的输入电压而不是调节器电路104的常规使用的输出VDD，而是使用比VDD高的电压的整流电路部分103的输出VDD0， 可以以小的电路面积获得将数据写入存储器所必需的。

公开(公告)号：US20110297939A1

公开(公告)日：2011-12-08

申请号：US13117603

申请日：2011-05-27

申请人： Kiyoshi KATO

发明人： Kiyoshi KATO

IPC分类号： H01L29/786 ,  H01L29/772

CPC分类号： H01L29/7869 ,  G11C16/0433 ,  G11C16/26 ,  H01L27/11517 ,  H01L27/1207 ,  H01L29/42384 ,  H01L29/78696

摘要： An object is to provide a semiconductor device having a novel structure with a high degree of integration. A semiconductor device includes a semiconductor layer having a channel formation region, a source electrode and a drain electrode electrically connected to the channel formation region, a gate electrode overlapping with the channel formation region, and a gate insulating layer between the channel formation region and the gate electrode. A portion of a side surface of the gate insulating layer and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other when seen from a planar direction.

摘要翻译： 目的在于提供具有高集成度的新型结构的半导体装置。 半导体器件包括具有沟道形成区域，与沟道形成区域电连接的源电极和漏电极的半导体层，与沟道形成区域重叠的栅极电极，以及沟道形成区域和沟道形成区域之间的栅极绝缘层 栅电极。 当从平面方向观察时，栅极绝缘层的侧表面的一部分和源电极或漏电极的侧表面的一部分基本上对准。

公开(公告)号：US20110297928A1

公开(公告)日：2011-12-08

申请号：US13117588

申请日：2011-05-27

申请人： Atsuo ISOBE ,  Yoshinori IEDA ,  Keitaro IMAI ,  Kiyoshi KATO ,  Yuto YAKUBO ,  Yuki HATA

发明人： Atsuo ISOBE ,  Yoshinori IEDA ,  Keitaro IMAI ,  Kiyoshi KATO ,  Yuto YAKUBO ,  Yuki HATA

IPC分类号： H01L27/105

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60

摘要： The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.

摘要翻译： 提供了一种半导体器件，其中包括第一晶体管，第二晶体管和电容器的多个存储单元被布置成矩阵，并且布线（也称为位线）用于连接其中一个存储单元和另一个 第一晶体管中的一个存储单元和源极或漏极区域通过导电层和设置在其间的第二晶体管中的源极或漏极电连接。 利用这种结构，与第一晶体管中的源极或漏极以及第二晶体管中的源极或漏极连接到不同布线的结构相比，可以减少布线的数量。 因此，可以提高半导体器件的集成度。

公开(公告)号：US20110254600A1

公开(公告)日：2011-10-20

申请号：US13173595

申请日：2011-06-30

申请人： Kiyoshi KATO ,  Takanori MATSUZAKI

发明人： Kiyoshi KATO ,  Takanori MATSUZAKI

IPC分类号： H03L7/08

CPC分类号： H03L7/0995 ,  H03L7/093 ,  H03L7/107 ,  H03L7/18

摘要： An object is to provide a PLL having a wide operating range. Another object is to provide a semiconductor device or a wireless tag which has a wide operating range in a communication distance or temperature by incorporating such a PLL. The semiconductor device or the wireless tag includes a first divider circuit; a second divider circuit; a phase comparator circuit to which an output of the first divider circuit and an output of the second divider circuit are provided; a loop filter to which an output of the phase comparator circuit is supplied and in which a time constant is switched in accordance with an inputted signal; and a voltage controlled oscillator circuit to which an output of the loop filter is supplied and which supplies an output to the second divider circuit.

摘要翻译： 目的是提供具有宽工作范围的PLL。 另一个目的是提供一种半导体器件或无线标签，其通过并入这种PLL而在通信距离或温度下具有宽的工作范围。 半导体器件或无线标签包括第一除法电路; 第二分频电路; 相位比较器电路，第一分频电路的输出和第二除法电路的输出端提供给该相位比较器电路; 环路滤波器，根据输入的信号，提供相位比较器电路的输出并将时间常数切换到该环路滤波器; 以及压控振荡器电路，所述环路滤波器的输出端被提供给所述压控振荡器电路，并将输出提供给所述第二除法电路。

公开(公告)号：US20110241008A1

公开(公告)日：2011-10-06

申请号：US13162791

申请日：2011-06-17

申请人： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Masahiko HAYAKAWA ,  Kiyoshi KATO ,  Mitsuaki OSAME ,  Takashi HIROSUE ,  Saishi FUJIKAWA

发明人： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Masahiko HAYAKAWA ,  Kiyoshi KATO ,  Mitsuaki OSAME ,  Takashi HIROSUE ,  Saishi FUJIKAWA

IPC分类号： H01L33/08

CPC分类号： H01L27/1244 ,  G02F1/136204 ,  H01L21/76804 ,  H01L21/76831 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/3244 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78621 ,  H01L29/78645 ,  H01L51/0037 ,  Y10S257/906 ,  Y10S257/908

摘要： A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is foamed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does. Thereafter, the gate insulating film and the two layers of the nitrogen-containing inorganic insulating films are partially etched away in the opening of the organic resin film to expose the active layer of the TFT.

摘要翻译： 具有层间绝缘膜的半导体显示装置，其中以有限的成膜时间确保表面水平度，用于除去水分的热处理不需要很长时间，并且防止层间绝缘膜中的水分逸出到邻近的膜或电极 层间绝缘膜。 形成TFT，然后形成与有机树脂膜相比传递较少水分的含氮无机绝缘膜，以覆盖TFT。 接下来，施加包含感光性丙烯酸树脂的有机树脂，并通过将有机树脂膜部分地曝光而形成开口。 然后将开口发泡的有机树脂膜用含有无机绝缘膜覆盖，所述无机绝缘膜比有机树脂膜透湿少。 此后，在有机树脂膜的开口部分将栅极绝缘膜和含氮无机绝缘膜的两层部分地蚀刻掉，以暴露TFT的有源层。

公开(公告)号：US20110068180A1

公开(公告)日：2011-03-24

申请号：US12889769

申请日：2010-09-24

申请人： Kiyoshi KATO

发明人： Kiyoshi KATO

IPC分类号： G06K19/07 ,  G06K19/067

CPC分类号： H01L27/1266 ,  H01L27/1214 ,  H01L27/13 ,  H01L29/78648

摘要： The size of a wireless chip is often determined according to an antenna circuit thereof. Power source voltage or power supplied to the wireless chip can be more easily received with a larger antenna. On the other hand, there has been an increasing demand for a compact wireless chip, and it is thus necessary to downsize an antenna. In view of this, the invention provides a wireless chip capable of data communication with a small antenna, namely a compact wireless chip having an improved communicable distance. A power source circuit of an ID chip of the invention generates a higher power source voltage than a power source voltage generated in a conventional ID chip, by using a boosting power source circuit having a boosting circuit and a rectifier circuit.

摘要翻译： 无线芯片的尺寸通常根据其天线电路来确定。 电源电压或提供给无线芯片的功率可以用更大的天线更容易地接收。 另一方面，对紧凑型无线芯片的需求日益增加，因此需要减小天线尺寸。 鉴于此，本发明提供了能够与小型天线进行数据通信的无线芯片，即具有改善的可通信距离的小型无线芯片。 本发明的ID芯片的电源电路通过使用具有升压电路和整流电路的升压电源电路产生比常规ID芯片中产生的电源电压更高的电源电压。

公开(公告)号：US20100055896A1

公开(公告)日：2010-03-04

申请号：US12618161

申请日：2009-11-13

申请人： Hiroko ABE ,  Mikio YUKAWA ,  Tamae TAKANO ,  Yoshinobu ASAMI ,  Kiyoshi KATO ,  Ryoji NOMURA ,  Yoshitaka MORIYA

发明人： Hiroko ABE ,  Mikio YUKAWA ,  Tamae TAKANO ,  Yoshinobu ASAMI ,  Kiyoshi KATO ,  Ryoji NOMURA ,  Yoshitaka MORIYA

IPC分类号： H01L21/3205

CPC分类号： H01L27/1266 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/04 ,  H01L27/12 ,  H01L27/1285 ,  H01L27/1292 ,  H01L27/13 ,  H01L27/283 ,  H01L51/0059

摘要： It is an object of the present invention to provide a volatile organic memory in which data can be written other than during manufacturing and falsification by rewriting can be prevented, and to provide a semiconductor device including such an organic memory. It is a feature of the invention that a semiconductor device includes a plurality of bit lines extending in a first direction; a plurality of word lines extending in a second direction different from the first direction; a memory cell array including a plurality of memory cells each provided at one of intersections of the bit lines and the word lines; and memory elements provided in the memory cells, wherein the memory elements include bit lines, an organic compound layer, and the word lines, and the organic compound layer includes a layer in which an inorganic compound and an organic compound are mixed.

摘要翻译： 本发明的一个目的是提供一种挥发性有机存储器，其中除了在制造期间可以写入数据，并且可以防止通过改写伪造，并提供包括这种有机存储器的半导体器件。 本发明的特征在于，半导体器件包括沿第一方向延伸的多个位线; 沿与第一方向不同的第二方向延伸的多个字线; 存储单元阵列，包括多个存储单元，每个存储单元分别设置在位线和字线的交点之一处; 以及设置在存储单元中的存储元件，其中存储元件包括位线，有机化合物层和字线，有机化合物层包括混合有无机化合物和有机化合物的层。

公开(公告)号：US20120139872A1

公开(公告)日：2012-06-07

申请号：US13367634

申请日：2012-02-07

申请人： Kiyoshi KATO ,  Toshihiko SAITO

发明人： Kiyoshi KATO ,  Toshihiko SAITO

IPC分类号： G09G3/36 ,  G06F3/045

CPC分类号： G02F1/13338 ,  G02F1/13306 ,  G02F1/133305 ,  G02F1/133345 ,  G02F1/13439 ,  G02F1/13454 ,  G02F1/136213 ,  G02F1/1368 ,  G02F2201/123 ,  G06F3/0412 ,  G06F3/044 ,  G09G3/36 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288 ,  H01L27/13 ,  H01L27/3244 ,  H01L29/78621 ,  H01L29/78645

摘要： A variable capacitor is formed from a pair of electrodes and a dielectric interposed between the electrodes over a substrate, and an external input is detected by changing capacitance of the variable capacitor by a physical or electrical force. Specifically, a variable capacitor and a sense amplifier are provided over the same substrate, and the sense amplifier reads the change of capacitance of the variable capacitor and transmits a signal in accordance with the input to a control circuit.

摘要翻译： 可变电容器由一对电极和位于基板之间的电极之间的电介质形成，并且通过用物理或电力改变可变电容器的电容来检测外部输入。 具体地说，在同一衬底上设置可变电容器和读出放大器，读出放大器读取可变电容器的电容变化，并根据输入将信号发送到控制电路。