公开(公告)号：US20110114941A1

公开(公告)日：2011-05-19

申请号：US12943532

申请日：2010-11-10

申请人： Kiyoshi KATO ,  Yoshinori IEDA ,  Jun KOYAMA

发明人： Kiyoshi KATO ,  Yoshinori IEDA ,  Jun KOYAMA

IPC分类号： H01L29/786

CPC分类号： H01L27/12 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/77 ,  H01L27/11521 ,  H01L27/1225 ,  H01L29/42324 ,  H01L29/7881

摘要： A device including a novel nonvolatile memory element is provided. A device including a nonvolatile memory element in which an oxide semiconductor is used as a semiconductor material for a channel formation region. The nonvolatile memory element includes a control gate, a charge accumulation layer which overlaps with the control gate with a first insulating film provided therebetween, and an oxide semiconductor layer formed using an oxide semiconductor material, which overlaps with the charge accumulation layer with a second insulating film provided therebetween.

摘要翻译： 提供了包括新颖的非易失性存储元件的装置。 包括其中使用氧化物半导体作为沟道形成区域的半导体材料的非易失性存储元件的器件。 非易失性存储元件包括控制栅极，与控制栅极重叠的电荷累积层，其间设置有第一绝缘膜，以及使用氧化物半导体材料形成的氧化物半导体层，其与电荷累积层重叠，具有第二绝缘 膜之间。

公开(公告)号：US20110297928A1

公开(公告)日：2011-12-08

申请号：US13117588

申请日：2011-05-27

申请人： Atsuo ISOBE ,  Yoshinori IEDA ,  Keitaro IMAI ,  Kiyoshi KATO ,  Yuto YAKUBO ,  Yuki HATA

发明人： Atsuo ISOBE ,  Yoshinori IEDA ,  Keitaro IMAI ,  Kiyoshi KATO ,  Yuto YAKUBO ,  Yuki HATA

IPC分类号： H01L27/105

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60

摘要： The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.

摘要翻译： 提供了一种半导体器件，其中包括第一晶体管，第二晶体管和电容器的多个存储单元被布置成矩阵，并且布线（也称为位线）用于连接其中一个存储单元和另一个 第一晶体管中的一个存储单元和源极或漏极区域通过导电层和设置在其间的第二晶体管中的源极或漏极电连接。 利用这种结构，与第一晶体管中的源极或漏极以及第二晶体管中的源极或漏极连接到不同布线的结构相比，可以减少布线的数量。 因此，可以提高半导体器件的集成度。

公开(公告)号：US20120112191A1

公开(公告)日：2012-05-10

申请号：US13270455

申请日：2011-10-11

申请人： Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Shuhei NAGATSUKA ,  Yuto YAKUBO ,  Jun KOYAMA

发明人： Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Shuhei NAGATSUKA ,  Yuto YAKUBO ,  Jun KOYAMA

IPC分类号： H01L29/16

CPC分类号： H01L27/1156 ,  G11C11/403 ,  G11C16/0433 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1225 ,  H01L28/40

摘要： A data retention period in a semiconductor device or a semiconductor memory device is lengthened. The semiconductor device or the semiconductor memory includes a memory circuit including a first transistor including a first semiconductor layer and a first gate and a second transistor including a second semiconductor layer, a second gate, and a third gate The first semiconductor layer is formed at the same time as a layer including the second gate.

摘要翻译： 半导体器件或半导体存储器件中的数据保持期延长。 半导体器件或半导体存储器包括存储电路，该存储器电路包括第一晶体管，其包括第一半导体层和第一栅极，第二晶体管包括第二半导体层，第二栅极和第三栅极。第一半导体层形成在 与包括第二门的层相同。

公开(公告)号：US20110285614A1

公开(公告)日：2011-11-24

申请号：US13197301

申请日：2011-08-03

申请人： Jun KOYAMA ,  Kiyoshi KATO

发明人： Jun KOYAMA ,  Kiyoshi KATO

IPC分类号： G09G3/36

CPC分类号： H04W52/027 ,  G02F1/13454 ,  G09G3/30 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G5/006 ,  G09G2300/0408 ,  G09G2300/08 ,  G09G2310/027 ,  G09G2330/022 ,  H01L27/12 ,  H01L27/1214 ,  Y02D70/00

摘要： A semiconductor device capable of displaying a still image with low consumption power is provided. In the semiconductor device incorporated with a semiconductor display device capable of displaying the still image, a memory portion is mounted on a substrate on which a pixel portion is formed. As a mounting method, the memory portion is formed on the substrate on which the pixel portion is formed or a stick driver including the memory portion is used. When the still image is displayed using image data stored in such a memory portion, the still image can be displayed by inputting only simple control signals from the outside of the semiconductor device. Thus, there are provided the semiconductor display device capable of displaying the still image with low consumption power and the semiconductor device incorporated with the semiconductor display device.

摘要翻译： 提供能够以低功耗显示静止图像的半导体器件。 在结合有能够显示静止图像的半导体显示装置的半导体装置中，存储部安装在形成有像素部的基板上。 作为安装方法，存储部形成在其上形成有像素部的基板上，或者使用包括存储部的棒驱动器。 当使用存储在这种存储器部分中的图像数据显示静止图像时，可以仅通过从半导体器件的外部输入简单的控制信号来显示静止图像。 因此，提供了能够以低功率功率显示静止图像的半导体显示装置以及并入半导体显示装置的半导体装置。

公开(公告)号：US20110122670A1

公开(公告)日：2011-05-26

申请号：US12947846

申请日：2010-11-17

申请人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

发明人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC分类号： G11C5/06

CPC分类号： G11C7/10 ,  G11C5/06 ,  G11C5/147 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/08 ,  G11C11/24 ,  G11C11/4097 ,  G11C16/0433 ,  G11C16/28 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/22 ,  H01L29/24 ,  H01L29/26 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

摘要： An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.

摘要翻译： 本发明的目的是提供一种半导体器件，其组合晶体管，其集成在其沟道形成区域中包括氧化物半导体的相同衬底晶体管和在其沟道形成区域中包括非氧化物半导体的晶体管。 本发明的应用是实现基本上不需要特定擦除操作的非易失性半导体存储器，并且不会因重复的写入操作而遭受损坏。 此外，半导体器件很适合于存储多值数据。 在说明书中详细说明制造方法，应用电路和驱动/读取方法。

公开(公告)号：US20090180326A1

公开(公告)日：2009-07-16

申请号：US12407539

申请日：2009-03-19

申请人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

发明人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC分类号： G11C16/06

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32

摘要： There is provided a non-volatile memory which enables high accuracy threshold control in a writing operation. In the present invention, a drain voltage and a drain current of a memory transistor are controlled to carry out a writing operation of a hot electron injection system, which is wherein a charge injection speed does not depend on a threshold voltage. FIGS. 1A and 1B are views of a circuit structure for controlling the writing. In FIGS. 1A and 1B, an output of an operational amplifier 103 is connected to a control gate of a memory transistor 101, a constant current source 102 is connected to a drain electrode, and a source electrode is grounded. The constant current source 102 and a voltage Vpgm are respectively connected to two input terminals of the operational amplifier 103.

摘要翻译： 提供了一种在写入操作中实现高精度阈值控制的非易失性存储器。 在本发明中，控制存储晶体管的漏极电压和漏极电流，进行热电子注入系统的写入动作，其中电荷注入速度不依赖于阈值电压。 图 图1A和1B是用于控制写入的电路结构的视图。 在图 如图1A和1B所示，运算放大器103的输出连接到存储晶体管101的控制栅极，恒流源102连接到漏电极，源电极接地。 恒流源102和电压Vpgm分别连接到运算放大器103的两个输入端。

公开(公告)号：US20110186949A1

公开(公告)日：2011-08-04

申请号：US13084996

申请日：2011-04-12

申请人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO ,  Takaaki KOEN ,  Yuto YAKUBO ,  Makoto YANAGISAWA ,  Hisashi OHTANI ,  Eiji SUGIYAMA ,  Nozomi HORIKOSHI

发明人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO ,  Takaaki KOEN ,  Yuto YAKUBO ,  Makoto YANAGISAWA ,  Hisashi OHTANI ,  Eiji SUGIYAMA ,  Nozomi HORIKOSHI

IPC分类号： H01L29/66

CPC分类号： G06K19/07735 ,  G06K19/07722 ,  G06K19/07794 ,  H01L23/295 ,  H01L23/3157 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

摘要： A semiconductor device capable of wireless communication, which has high reliability in terms of resistance to external force, in particular, pressing force and can prevent electrostatic discharge in an integrated circuit without preventing reception of an electric wave. The semiconductor device includes an on-chip antenna connected to the integrated circuit and a booster antenna which transmits a signal or power included in a received electric wave to the on-chip antenna without contact. In the semiconductor device, the integrated circuit and the on-chip antenna are interposed between a pair of structure bodies formed by impregnating a fiber body with a resin. One of the structure bodies is provided between the on-chip antenna and the booster antenna. A conductive film having a surface resistance value of approximately 106 to 1014 Ω/cm2 is formed on at least one surface of each structure body.

摘要翻译： 一种能够进行无线通信的半导体装置，其在外力方面具有高的可靠性，特别是按压力，并且能够防止集成电路中的静电放电，而不会妨碍电波的接收。 半导体器件包括连接到集成电路的片上天线和将接收到的电波中包含的信号或功率发送到片上天线而不接触的增强天线。 在半导体器件中，集成电路和片上天线插入通过用树脂浸渍纤维体而形成的一对结构体之间。 其中一个结构体设置在片上天线和增强天线之间。 在每个结构体的至少一个表面上形成表面电阻值为大约106至1014Ω·cm 2 / cm 2的导电膜。

公开(公告)号：US20110101334A1

公开(公告)日：2011-05-05

申请号：US12912190

申请日：2010-10-26

申请人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

发明人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC分类号： H01L27/108

CPC分类号： H01L27/088 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1225

摘要： It is an object to provide a semiconductor having a novel structure. In the semiconductor device, a plurality of memory elements are connected in series and each of the plurality of memory elements includes first to third transistors thus forming a memory circuit. A source or a drain of a first transistor which includes an oxide semiconductor layer is in electrical contact with a gate of one of a second and a third transistor. The extremely low off current of a first transistor containing the oxide semiconductor layer allows storing, for long periods of time, electrical charges in the gate electrode of one of the second and the third transistor, whereby a substantially permanent memory effect can be obtained. The second and the third transistors which do not contain an oxide semiconductor layer allow high-speed operations when using the memory circuit.

摘要翻译： 本发明的目的是提供具有新颖结构的半导体。 在半导体器件中，多个存储器元件串联连接，并且多个存储元件中的每一个包括第一至第三晶体管，从而形成存储器电路。 包括氧化物半导体层的第一晶体管的源极或漏极与第二和第三晶体管之一的栅极电接触。 含有氧化物半导体层的第一晶体管的极低的截止电流允许长时间地在第二和第三晶体管之一的栅电极中存储电荷，由此可以获得基本上永久的记忆效应。 不含氧化物半导体层的第二和第三晶体管在使用存储电路时允许高速操作。

公开(公告)号：US20100253478A1

公开(公告)日：2010-10-07

申请号：US12754416

申请日：2010-04-05

申请人： Jun KOYAMA ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

发明人： Jun KOYAMA ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

IPC分类号： H04Q5/22

CPC分类号： H04W52/028 ,  Y02D70/122 ,  Y02D70/166

摘要： An object is to provide a data processing device which achieves multiple functions or easy additional providing of a function while suppressing adverse influence on a communication distance or to improve resistance to electrostatic discharge in the data processing device. The data processing device includes an antenna which transmits and receives a first signal to/from a first terminal device through wireless communication, an integrated circuit which executes a process in accordance with the first signal, and a terminal portion which transmits and receives a second signal to/from a second terminal device and has an exposed conductive portion on its surface. A protection circuit is provided between at least one terminal of terminals of the terminal portion and a power supply terminal of a high potential and between the one terminal and a power supply terminal of a low potential.

摘要翻译： 本发明的目的是提供一种能够实现多种功能的数据处理装置，或容易地附加提供功能，同时抑制对通信距离的不利影响或提高数据处理装置中的静电放电的抵抗力。 数据处理装置包括通过无线通信向第一终端装置发送第一信号的接收天线，执行与第一信号对应的处理的集成电路以及发送接收第二信号的终端部 到/从第二终端设备，并且在其表面上具有暴露的导电部分。 在端子部分的端子的至少一个端子和高电位的电源端子之间以及在一个端子和低电位的电源端子之间提供保护电路。

公开(公告)号：US20100245306A1

公开(公告)日：2010-09-30

申请号：US12796067

申请日：2010-06-08

申请人： Jun KOYAMA ,  Kiyoshi KATO

发明人： Jun KOYAMA ,  Kiyoshi KATO

IPC分类号： G09G5/00

CPC分类号： H04W52/027 ,  G02F1/13454 ,  G09G3/30 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G5/006 ,  G09G2300/0408 ,  G09G2300/08 ,  G09G2310/027 ,  G09G2330/022 ,  H01L27/12 ,  H01L27/1214 ,  Y02D70/00

摘要： A semiconductor device capable of displaying a still image with low consumption power is provided. In the semiconductor device incorporated with a semiconductor display device capable of displaying the still image, a memory portion is mounted on a substrate on which a pixel portion is formed. As a mounting method, the memory portion is formed on the substrate on which the pixel portion is formed or a stick driver including the memory portion is used. When the still image is displayed using image data stored in such a memory portion, the still image can be displayed by inputting only simple control signals from the outside of the semiconductor device. Thus, there are provided the semiconductor display device capable of displaying the still image with low consumption power and the semiconductor device incorporated with the semiconductor display device.

摘要翻译： 提供能够以低功耗显示静止图像的半导体器件。 在结合有能够显示静止图像的半导体显示装置的半导体装置中，存储部安装在形成有像素部的基板上。 作为安装方法，存储部形成在其上形成有像素部的基板上，或者使用包括存储部的棒驱动器。 当使用存储在这种存储器部分中的图像数据显示静止图像时，可以仅通过从半导体器件的外部输入简单的控制信号来显示静止图像。 因此，提供了能够以低功率功率显示静止图像的半导体显示装置以及并入半导体显示装置的半导体装置。