公开(公告)号：US20240047227A1

公开(公告)日：2024-02-08

申请号：US18446428

申请日：2023-08-08

Applicant: Zhuhai ACCESS Semiconductor Co., LTD.

Inventor： Xianming CHEN ,  Wenjian LIN ,  Benxia HUANG ,  Gao HUANG

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/02 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L21/568 ,  H01L21/486 ,  H01L21/02491 ,  H01L24/11 ,  H01L23/49822 ,  H01L24/16 ,  H01L23/49838 ,  H01L21/02631 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/11001 ,  H01L2224/1145 ,  H01L2224/16235 ,  H01L2924/182 ,  H01L2924/01029

Abstract: A package substrate with an embedded device and a manufacturing method therefor are disclosed. The method includes: manufacturing a third circuit layer and a target on a temporary carrier plate, and laminating a third dielectric layer; placing a device to be embedded on the third dielectric layer which is then covered with a second dielectric layer; laminating a second copper foil and manufacturing a second circuit layer, a second copper pillar, and a third copper pillar; laminating a first dielectric layer and a first copper foil sequentially, and removing the temporary carrier plate; laminating a fourth dielectric layer on the third circuit layer; laminating a fourth copper foil on the fourth dielectric layer; and manufacturing a fourth circuit layer and a fourth copper pillar through the fourth copper foil, and manufacturing a first circuit layer and a first copper pillar through the first copper foil.

公开(公告)号：US20230199957A1

公开(公告)日：2023-06-22

申请号：US17906853

申请日：2020-07-24

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd.

Inventor： Xianming CHEN ,  Lei FENG ,  Benxia HUANG ,  Yejie HONG

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/18 ,  H05K3/46

CPC classification number: H05K1/115 ,  H05K3/0047 ,  H05K3/0076 ,  H05K3/188 ,  H05K3/4658 ,  H05K2201/096 ,  H05K2201/09545 ,  H05K2203/061 ,  H05K2203/0723 ,  H05K2203/167

Abstract: A multilayer substrate and a manufacturing method thereof are disclosed. The multilayer substrate includes two or more dielectric layers laminated in sequence; a public line disposed at a top or bottom dielectric layer of the two or more dielectric layers; and two or more first through hole pillars respectively each embedded in a respective one of the dielectric layers, and the first through hole pillars are connected in cascade and then connected with the public line.

公开(公告)号：US20230197739A1

公开(公告)日：2023-06-22

申请号：US17998159

申请日：2020-07-24

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd.

Inventor： Xianming CHEN ,  Lei FENG ,  Weiyuan YANG ,  Benxia HUANG ,  Yejie HONG

IPC: H01L27/13

CPC classification number: H01L27/13 ,  H01L28/10 ,  H01L28/40

Abstract: A capacitor and inductor embedded structure and a manufacturing method therefor, and a substrate are disclosed. The method includes: providing a metal plate; sequentially depositing and etching a first protective layer, a thin film dielectric layer, a second protective layer, and an upper electrode layer on an upper surface of the metal plate to form a thin film capacitor and a capacitor upper electrode; pressing an upper dielectric layer to the upper surface of the metal plate, covering the thin film capacitor and the capacitor upper electrode, and etching the metal plate to form a capacitor lower electrode; pressing a lower dielectric layer to a lower surface of the metal plate, and performing drilling on the upper dielectric layer and the lower dielectric layer to form inductor through holes and capacitor electrode through holes; electroplating metal to form an inductor and circuit layers.

公开(公告)号：US20230051730A1

公开(公告)日：2023-02-16

申请号：US17976228

申请日：2022-10-28

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Yejie HONG ,  Benxia HUANG ,  Lei FENG

IPC: H01L23/538 ,  H01L21/50 ,  H01L21/768 ,  H01L23/15 ,  H01L23/00

Abstract: A package substrate includes: a glass frame having a through hole and a chip embedding cavity; an electronic component arranged in the chip embedding cavity; a dielectric layer filled on an upper surface of the glass frame and in the chip embedding cavity; a metal pillar passing through the through hole; a circuit layer arranged on the upper surface and/or a lower surface of the glass frame and connected to the electronic component and the metal pillar; and a solder mask arranged on a surface of the circuit layer and having a pad which is connected to the circuit layer.

公开(公告)号：US20210410297A1

公开(公告)日：2021-12-30

申请号：US17038898

申请日：2020-09-30

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Jian PENG ,  Jida ZHANG ,  Benxia HUANG ,  Lei FENG ,  Bingsen XIE ,  Jun GAO

IPC: H05K3/46

Abstract: A temporary carrier according to an embodiment of the present invention may include a core layer, a first Cu foil layer and a second Cu foil layer on surfaces of both sides of the core layer. Each of the first Cu foil layer and the second Cu foil layer may include double Cu foils which are physically attached together.

公开(公告)号：US20210391213A1

公开(公告)日：2021-12-16

申请号：US17073968

申请日：2020-10-19

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Min GU ,  Benxia HUANG ,  Lei FENG ,  Bingsen XIE

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/48 ,  H01L23/48 ,  H01L23/14

Abstract: A method for manufacturing an interposer board without a feature layer structure according to an embodiment of the present invention may include preparing a temporary carrier; forming an edge seal for the temporary carrier; laminating an insulating material onto upper and lower surfaces of the temporary carrier to form an insulating layer; forming a via on the insulating layer, filling the via with a metal; and removing the edge seal and removing the temporary carrier. An interposer board without a feature layer structure according to an embodiment of the present invention may include an insulating layer and a via-post layer embedded in the insulating layer, wherein the via-post has an end used as a pad.

公开(公告)号：US20240321594A1

公开(公告)日：2024-09-26

申请号：US18612661

申请日：2024-03-21

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd.

Inventor： Xianming CHEN ,  Xiaowei XU ,  Yejie HONG ,  Benxia HUANG ,  Gao HUANG ,  Dongfeng ZHANG ,  Jindong FENG

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49827 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68345 ,  H01L2224/24155 ,  H01L2224/82106

Abstract: An embedded magnet frame, an integrated structure and a manufacturing method are disclosed. The manufacturing method includes: manufacturing conductive metal columns, a first sacrificial block and a second sacrificial block on a surface of a bearing plate; laminating a first dielectric layer on the surface of the bearing plate so that the first dielectric layer covers the conductive metal columns, the first sacrificial block and the second sacrificial block; thinning the first dielectric layer to expose surfaces of the conductive metal columns, the first sacrificial block and the second sacrificial block; etching the first sacrificial block and the second sacrificial block to form corresponding first and second mounting cavities, the second mounting cavity being used for mounting a chip; filling the first mounting cavity with magnetic slurry to form an embedded magnet; and removing the bearing plate to form an embedded magnet frame.

公开(公告)号：US20240079287A1

公开(公告)日：2024-03-07

申请号：US18453185

申请日：2023-08-21

Applicant: Zhuhai ACCESS Semiconductor Co., LTD.

Inventor： Xianming CHEN ,  Xiaowei XU ,  Juchen HUANG ,  Gao HUANG ,  Benxia HUANG ,  Chaobiao QIN

IPC: H01L23/367 ,  H01L21/48

CPC classification number: H01L23/367 ,  H01L21/4857 ,  H01L21/4871

Abstract: A method for manufacturing a high-heat-dissipation mixed substrate includes: preparing a mother substrate, the mother substrate including an insulating layer and a temporary carrier plate which are laminated; arranging a plurality of first grooves and a plurality of first cavities on the mother substrate; filling the first groove with a thermally-conductive material to form a first thermally-conductive block, and adhering an embedded device in the first cavity and filling the first cavity with the thermally-conductive material to form a second thermally-conductive block; removing the temporary carrier plate to obtain a semi-finished substrate; manufacturing circuit layers on two opposite side surfaces of the semi-finished substrate to obtain a target mother substrate; and cutting the target mother substrate along region dividing lines to obtain a mixed substrate with a side surface being a thermally-conductive surface.

公开(公告)号：US20230276576A1

公开(公告)日：2023-08-31

申请号：US18174619

申请日：2023-02-25

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd.

Inventor： Xianming CHEN ,  Wenjian LIN ,  Gao HUANG ,  Lei FENG ,  Jindong FENG ,  Benxia HUANG ,  Zhijun ZHANG

IPC: H05K1/18 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H05K1/11 ,  H05K3/42 ,  H05K3/10 ,  H05K3/30

CPC classification number: H05K1/186 ,  H01L21/56 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/20 ,  H05K1/113 ,  H05K3/423 ,  H05K3/108 ,  H05K3/305 ,  H01L2224/19 ,  H01L2224/2101 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K3/0023

Abstract: A package substrate and a manufacturing method thereof are disclosed. The method includes: providing an inner substrate; processing an adhesive photosensitive material on a surface of a first side of the inner substrate to obtain an adhesive first insulating dielectric layer; mounting a component on the first insulating dielectric layer; and processing a photosensitive packaging material on the first side of the inner substrate to obtain a second insulating dielectric layer, where the second insulating dielectric layer covers the component.

公开(公告)号：US20230232545A1

公开(公告)日：2023-07-20

申请号：US18145349

申请日：2022-12-22

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd.

Inventor： Xianming CHEN ,  Lei FENG ,  Benxia HUANG ,  Wenjian LIN ,  Gao HUANG

IPC: H05K3/46 ,  H05K1/18 ,  H05K3/00

CPC classification number: H05K3/4644 ,  H05K1/185 ,  H05K3/0047 ,  H05K3/4697

Abstract: A method for manufacturing a packaging substrate, and a packaging substrate are disclosed. The method includes: providing a bottom board with a first circuit layer, the first circuit layer being provided with at least one demand point, and one side of the demand point being provided with a first to-be-avoided region; machining a first intermediate insulating layer on the bottom board, the first intermediate insulating layer including a first intermediate insulating dielectric covering the first to-be-avoided region; machining a first intermediate wiring layer on the first intermediate insulating layer, the first intermediate wiring layer including a first intermediate circuit partially arranged on the first intermediate insulating dielectric and connected to the demand point; machining a first insulating layer on the first intermediate wiring layer which is stacked on the bottom board and covers the first intermediate wiring layer; and machining a circuit build-up layer on the first insulating layer.