公开(公告)号：US09985640B1

公开(公告)日：2018-05-29

申请号：US15793839

申请日：2017-10-25

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Gordon Ueki

IPC: H03M1/38 ,  H03M1/10 ,  H03M1/46

CPC classification number: H03M1/1009 ,  H03M1/462 ,  H03M1/466

Abstract: The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.

公开(公告)号：US09967647B2

公开(公告)日：2018-05-08

申请号：US14850859

申请日：2015-09-10

Applicant: Avnera Corporation

Inventor： Amit Kumar ,  Eric Sorensen ,  Shankar Rathoud

IPC: H04R1/10 ,  G10K11/178 ,  H04R3/00 ,  H04R29/00

CPC classification number: H04R1/1041 ,  G10K11/178 ,  G10K11/17855 ,  G10K2210/1081 ,  G10K2210/3021 ,  H04R1/1083 ,  H04R3/00 ,  H04R29/00 ,  H04R2410/05 ,  H04R2460/03

Abstract: A headphone detector including a headphone and a processor. The headphone has a microphone and a speaker, and the microphone is configured to generate an audio signal based on an output of the speaker. The processor is configured to receive the audio signal, determine a characteristic of the audio signal, and assess whether the headphone is on ear or off ear based on a comparison of the characteristic to a threshold. In another aspect, an off-ear detection (OED) system includes a headphone and an OED processor. The headphone has a speaker, a feedforward microphone, and a feedback microphone. The OED processor is configured to determine whether the headphone is off ear or on ear, based at least in part on a headphone audio signal, a feedforward microphone signal, and a feedback microphone signal.

公开(公告)号：US09520893B1

公开(公告)日：2016-12-13

申请号：US15067500

申请日：2016-03-11

Applicant: AVNERA CORPORATION

Inventor： Christopher D. Nilson

IPC: H03M1/06 ,  H03M1/66 ,  G05F3/26 ,  H03M1/00 ,  H03M1/74 ,  H03M1/12

CPC classification number: H03M1/747 ,  G05F3/262 ,  H03M1/00 ,  H03M1/12 ,  H03M1/68

Abstract: A current-mode, digital-to-analog converter (DAC) configured to convert a digital word input having j bits to an analog signal. The DAC has 2j current sources, an output node, a current divider, a first switch, and a second switch. Each of the 2j current sources is configured to produce a current having a value I0. The current divider has a programmable divide ratio, d, where 1/d is between 0 and 1. The first switch is configured to selectively couple 2j−1 of the 2j current sources to the output node. One of the 2j current sources is not coupled to the output node. The second switch is configured to selectively couple each of the 2j current sources to the current divider. This architecture ensures that the fundamental transform of input code to output current always has a slope that does not change from positive to negative or from negative to positive.

Abstract translation: 电流模式的数模转换器（DAC），被配置为将具有j位的数字字输入转换为模拟信号。 DAC具有2j电流源，输出节点，分流器，第一开关和第二开关。 每个2j电流源被配置为产生具有值I0的电流。 电流分压器具有可编程分频比d，其中1 / d在0和1之间。第一开关被配置为选择性地将2j电流源的2j-1耦合到输出节点。 2j电流源中的一个未耦合到输出节点。 第二开关被配置为选择性地将2j电流源中的每一个耦合到电流分配器。 这种架构确保输入代码对输出电流的基本变换总是具有不会从正变化到负变化或从负变为正的斜率。

公开(公告)号：US20160140983A1

公开(公告)日：2016-05-19

申请号：US14857681

申请日：2015-09-17

Applicant: AVNERA CORPORATION

Inventor： Xudong Zhao

IPC: G10L21/043 ,  G10L19/008 ,  G10L21/0232 ,  G10L19/02 ,  G10L19/24 ,  G10L21/0224

CPC classification number: H03H17/0628 ,  G10L19/00 ,  G10L19/24 ,  G10L21/0316 ,  G10L21/0356 ,  G10L2019/001 ,  H03H17/028 ,  H03M5/00 ,  H03M7/00 ,  H03M13/00 ,  H03M13/27 ,  H03M13/33

Abstract: Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

Abstract translation: 本发明的实施例可以用于实现速率转换器，其包括：正向（音频）路径中的6个信道，每个信道具有每信道24位信号路径，110dB的端到端SNR，全部在 20 Hz至20 KHz带宽。 实施例还可以用于实现速率转换器，其具有：在反向路径中的2个信道，例如用于语音信号，每信道16位信号路径，93dB的端到端SNR，均在20Hz至20 KHz带宽。 速率转换器可以包括诸如8,11.025,12,16,22.05,24,34,44,48和96KHz的采样率。 此外，根据实施例的速率转换器可以包括低功率模式的门控时钟以节省功率。

公开(公告)号：US20140219490A1

公开(公告)日：2014-08-07

申请号：US14231664

申请日：2014-03-31

Applicant: Avnera Corporation

Inventor： Patrick A. Quinn ,  Robert C. Proebstel ,  Manpreet S. Khaira ,  Thomas Irrgang ,  Nigel D. Waites ,  Ian J. Myles

IPC: H04R1/32

CPC classification number: H04R1/32 ,  H04R1/026 ,  H04R1/2803 ,  H04R3/005 ,  H04R29/00 ,  H04R2225/33 ,  H04R2400/03 ,  H04R2420/07

Abstract: An acoustic layer is added to a laptop-type personal computing device, comprising: enclosing walls, optionally—one or more microphones, a signal processing device, at least one audio transducer, and an acoustic waveguide. The acoustic layer adjoins one or more internal areas of a laptop-type device. The signal processing device receives an internal signal from a laptop-type device. The signal processing device provides a directive sound enhancement of the audio input signals based on room acoustics, such as reverberation, echo, noise, delay, frequency response, and/or speaker-positional information that is determined by the signal processing device. The audio transducer device generates an audible audio output in response to an audio signal output from the signal processing device. The acoustic waveguide receives the audible audio output and generates an enhanced bass audio output from the acoustic waveguide.

Abstract translation: 声学层被添加到笔记本电脑型个人计算设备中，包括：封闭墙壁，可选地一个或多个麦克风，信号处理设备，至少一个音频换能器和声波导。 声学层邻接膝上型设备的一个或多个内部区域。 信号处理装置从笔记本电脑型装置接收内部信号。 信号处理装置基于由信号处理装置确定的诸如混响，回波，噪声，延迟，频率响应和/或扬声器位置信息的房间声学来提供音频输入信号的指令声音增强。 音频换能器装置响应于从信号处理装置输出的音频信号产生可听音频输出。 声波导接收可听音频输出，并从声波导产生增强的低音音频输出。

公开(公告)号：US20070238490A1

公开(公告)日：2007-10-11

申请号：US11279340

申请日：2006-04-11

Applicant: Mats MYRBERG ,  Manpreet Khaira

Inventor： Mats MYRBERG ,  Manpreet Khaira

IPC: H04M1/00

CPC classification number: H04M1/6066 ,  H04M1/6008 ,  H04R3/005 ,  H04R2420/07 ,  H04R2430/20

Abstract: A wireless communication system includes a wireless terminal and a host device. The wireless terminal includes a transceiver and a processor. The transceiver of the wireless terminal transmits electrical audio signals output from a plurality of microphones over a wireless communication link for enhancement processing, such as noise-cancellation processing, echo-cancellation processing, and/or sidetone processing, at the host device. The wireless communication link can be an electromagnetic-based wireless communication link, a light-based wireless communication link and/or a magnetic-induction-based wireless communication link. The transceiver of the wireless terminal further receives from the wireless communication link enhancement-processed signals based on the electrical audio signals. The processor of the wireless terminal uses the enhancement-processed signals to output an enhanced audio output signal from the terminal device.

Abstract translation: 无线通信系统包括无线终端和主机设备。 无线终端包括收发机和处理器。 无线终端的收发机通过无线通信链路发送从多个麦克风输出的电音频信号，以在主机设备处进行诸如噪声消除处理，回波消除处理和/或侧音处理之类的增强处理。 无线通信链路可以是基于电磁的无线通信链路，基于光的无线通信链路和/或基于磁感应的无线通信链路。 无线终端的收发机还基于电音频信号从无线通信链路接收增强处理的信号。 无线终端的处理器使用增强处理的信号从终端设备输出增强的音频输出信号。

公开(公告)号：US20070182447A1

公开(公告)日：2007-08-09

申请号：US11341337

申请日：2006-01-26

Applicant: Patrick Quinn

Inventor： Patrick Quinn

IPC: H03K19/094

CPC classification number: H03K19/018521

Abstract: A circuit architecture, or topology, that provides a level shifter which is substantially independent of the duty cycle of an input signal includes an H-bridge arrangement of field effect transistors, a pair of capacitively coupled inputs terminals connected to the gates of the high-side (i.e., connected to the positive power supply) transistors and a pair of voltage dividers to set the bias voltage at the gates of the high-side transistors, wherein one side of each voltage divider is coupled to the power supply node and the other side of each voltage divider is cross-coupled to the output node of the opposite side of the H-bridge.

Abstract translation: 提供基本上独立于输入信号的占空比的电平移位器的电路架构或拓扑结构包括场效应晶体管的H桥布置，连接到高电平的栅极的一对电容耦合的输入端子， （即，连接到正电源）晶体管和一对分压器，以在高侧晶体管的栅极处设置偏置电压，其中每个分压器的一侧耦合到电源节点，而另一侧耦合到电源节点 每个分压器的一侧交叉耦合到H桥的相对侧的输出节点。

公开(公告)号：US07215269B2

公开(公告)日：2007-05-08

申请号：US11249236

申请日：2005-10-12

Applicant: Wai L. Lee ,  Xudong Zhao ,  Amit Kumar ,  Jianping Wen ,  Garry N Link

Inventor： Wai L. Lee ,  Xudong Zhao ,  Amit Kumar ,  Jianping Wen ,  Garry N Link

IPC: H03M3/00

CPC classification number: H03M3/452 ,  H03H11/04 ,  H03H17/0664 ,  H03H2218/04 ,  H03H2218/10 ,  H03M3/424 ,  H03M3/448 ,  H03M3/454 ,  H03M3/462

Abstract: A radio receiver channel includes an analog front end and a digital signal processing section coupled together by an analog-to-digital converter (ADC) having a delta-sigma modulator coupled to a first digital decimation filter, which is coupled to second digital decimation filter, wherein the first decimation filter includes a source of finite impulse response coefficients coupled so as to provide a plurality of coefficients. The delta-sigma modulator includes a loop filter having a plurality of serially coupled integrators, and a multi-bit quantizer coupled to the loop filter; the multi-bit quantizer including an ADC operable to produce a multi-bit digital output signal, the ADC coupled to a DAC having dual DAC feedback loops, and a dynamic element matching function. In one embodiment, the delta-sigma modulator includes a fifth-order loop filter having five serially coupled integrators with a feedback path from the output to the input of the fifth integrator and a feedback path from the output to the input of the third integrator.

公开(公告)号：US11056093B2

公开(公告)日：2021-07-06

申请号：US16446064

申请日：2019-06-19

Applicant: Avnera Corporation

Inventor： James Scanlan

IPC: H04R1/10 ,  G10K11/178 ,  H04R1/40 ,  H04R3/00 ,  H04R29/00

Abstract: The disclosure includes a headset comprising one or more earphones including one or more sensing components. The headset also includes one or more voice microphones to record a voice signal for voice transmission. The headset also includes a signal processor coupled to the earphones and the voice microphones. The signal processor is configured to employ the sensing components to determine a wearing position of the headset. The signal processor then selects a signal model for noise cancellation. The signal model is selected from a plurality of signal models based on the determined wearing position. The signal processor also applies the selected signal model to mitigate noise from the voice signal prior to voice transmission.

公开(公告)号：US11032631B2

公开(公告)日：2021-06-08

申请号：US16505554

申请日：2019-07-08

Applicant: Avnera Corporation

Inventor： Deepika Kumari ,  Colin Michael Doolittle ,  Amit Kumar

IPC: H04R1/10 ,  H04R3/04 ,  H04R3/00 ,  H04R29/00 ,  H04R1/40 ,  G10L25/21 ,  G10K11/175

Abstract: Disclosed is a signal processor for headphone off-ear detection. The signal processor includes an audio output to transmit an audio signal toward a headphone speaker in a headphone cup. The signal processor also includes a feedback (FB) microphone input to receive a FB signal from a FB microphone in the headphone cup. The signal processor also includes an off-ear detection (OED) signal processor to determine an audio frequency response of the FB signal over an OED frame as a received frequency response. The OED processor also determines an audio frequency response of the audio signal times an off-ear transfer function between the headphone speaker and the FB microphone as an ideal off-ear response. A difference metric is generated comparing the received frequency response to the ideal off-ear frequency response. The difference metric is employed to detect when the headphone cup is disengaged from an ear.