-
公开(公告)号：US20240186318A1
公开(公告)日：2024-06-06
申请号：US18526384
申请日：2023-12-01
发明人： Christian RIVERO , Joel METZ , Brice ARRAZAT
IPC分类号： H01L27/06 , H01L29/423 , H01L29/66 , H01L29/94
CPC分类号： H01L27/0629 , H01L29/42336 , H01L29/66181 , H01L29/945
摘要： An integrated circuit includes a capacitive transistor supported by a semiconductor substrate. The capacitive transistor includes: a drain and a source formed in the semiconductor substrate; a gate having a first portion extending in depth in the semiconductor substrate, and a second portion prolonging said first portion and extending over the semiconductor substrate; and a dielectric layer extending between the gate and the semiconductor substrate.
-
公开(公告)号：US11967900B2
公开(公告)日：2024-04-23
申请号：US17366353
申请日：2021-07-02
发明人： Sebastien Ortet , Olivier Lauzier
CPC分类号： H02M3/158 , H02M1/0032 , H02M1/0083 , H02M1/36
摘要： An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator including first and second inputs. The first input is configured to receive, during a first phase, a first voltage ramp and, during a second phase, a set point voltage. The second input is configured to receive, during the first phase, the set point voltage and, during the second phase, a second voltage ramp.
-
13.发明授权公开(公告)号：US11943931B2
公开(公告)日：2024-03-26
申请号：US17220286
申请日：2021-04-01
摘要： In one embodiment, a non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.
-
公开(公告)号：US20240095502A1
公开(公告)日：2024-03-21
申请号：US18470281
申请日：2023-09-19
发明人： Pierre Demaj , Laurent Folliot
IPC分类号： G06N3/0464
CPC分类号： G06N3/0464
摘要： An artificial neural network includes a unit cell. The unit cell includes a first binary two-dimensional convolution layer configured to receive an input tensor and to generate a first tensor. A first batch normalization layer is configured to receive the first tensor and to generate a second tensor. A concatenation layer is configured to generate a third tensor by concatenating the input tensor and the second tensor. A second binary two-dimensional convolution layer is configured to receive the third tensor and to generate a fourth tensor. A second batch normalization layer is configured to generate an output tensor based on the fourth tensor.
-
公开(公告)号：US20240081160A1
公开(公告)日：2024-03-07
申请号：US18506383
申请日：2023-11-10
发明人： Philippe BOIVIN , Simon JEANNOT
CPC分类号： H10N70/231 , H10B63/30 , H10B63/80 , H10N70/011 , H10N70/061 , H10N70/253 , H10N70/823 , H10N70/826 , H10N70/8265 , H10N70/8413 , H10N70/8828 , G11C13/0004
摘要： A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
-
公开(公告)号：US11921834B2
公开(公告)日：2024-03-05
申请号：US16249804
申请日：2019-01-16
发明人： Fabrice Marinet
CPC分类号： G06F21/44 , B41J2/17546 , B41J2/17566 , G06K15/1822 , G06F21/73 , G06F2221/2129
摘要： A method of authenticating a first electronic circuit includes generating a first signature using the first electronic circuit, the generating of the first signature being based on states of a plurality of electric nodes distributed within the first electronic circuit. A second signature is generated using a second electronic circuit, the generating of the second signature being based on states of a plurality of electric nodes distributed within the second electronic circuit. The first signature is compared to the second signature. The first electronic circuit is authenticated based on the comparison of the first signature to the second signature.
-
公开(公告)号：US11894657B2
公开(公告)日：2024-02-06
申请号：US17360381
申请日：2021-06-28
发明人： Romeo Letor , Vanni Poletto , Antoine Pavlin , Nadia Lecci , Alfio Russo
CPC分类号： H01S5/06216 , H01S5/0261 , H03K5/07
摘要： An embodiment pulse generator circuit comprises a first electronic switch coupled between first and second nodes, and a second electronic switch coupled between the second node and a reference node. An LC resonant circuit comprising an inductance and a capacitance is coupled between the first and reference nodes along with charge circuitry comprises a further inductance in a current flow line between a supply node and an intermediate node in the LC resonant circuit. Drive circuitry of the electronic switches repeats, during a sequence of switching cycles, charge time intervals, wherein the capacitance in the LC resonant circuit is charged via the charge circuit, and pulse generation time intervals, wherein a pulsed current is provided to the load via the first and second nodes. The charge and pulse generation time intervals are interleaved with oscillation time intervals where the LC resonant circuit oscillates at a resonance frequency.
-
公开(公告)号：US11889397B2
公开(公告)日：2024-01-30
申请号：US17649146
申请日：2022-01-27
CPC分类号： H04W4/80 , G06K7/0008 , G06K7/10237 , G06K7/10247 , H04B5/0031
摘要： A device, including a main element and a set of at least two auxiliary elements, said main element including a master SWP interface, each auxiliary element including a slave SWP interface connected to said master SWP interface of said NFC element through a controllably switchable SWP link and management means configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.
-
公开(公告)号：US11855633B2
公开(公告)日：2023-12-26
申请号：US17827515
申请日：2022-05-27
发明人： Jean-Francois Link , Mark Wallis , Joran Pantel
IPC分类号： H03K19/17724 , H03K19/173 , H03K19/17704 , H03K3/0233 , H03K19/096
CPC分类号： H03K19/17724 , H03K3/0233 , H03K19/096 , H03K19/1737 , H03K19/17708
摘要： An integrated circuit includes a programmable logic array. The programmable logic array incudes a plurality of logic elements arranged in rows and columns. Each logic element includes a direct output and a synchronized output. The direct output of each logic element is coupled to all other logic elements of higher rank, but is not coupled to logic elements of lower rank.
-
20.发明公开公开(公告)号：US20230401306A1
公开(公告)日：2023-12-14
申请号：US18207292
申请日：2023-06-08
发明人： Laurent TABARIES
摘要： The electronic control unit includes a communication circuit adapted to receive intelligent transport system messages, an authentication circuit designed to authenticate the received messages, a non-volatile memory configured to record the authenticated received messages, and a secure element. The secure element includes a blacklist of automatically excluded senders and is configured to directly reject a received message from a sender on the blacklist without authentication using the authentication circuit. Alternatively, the secure element includes a whitelist of automatically allowed senders and is configured to directly record a received message from a sender on the whitelist in the non-volatile memory without authentication using the authentication circuit.
-
-
-
-
-
-
-
-
-
搜索结果
1599 条记录 (耗时 0.027 秒)
