公开(公告)号：US07202549B2

公开(公告)日：2007-04-10

申请号：US10848384

申请日：2004-05-19

Applicant: Yasunori Hashimoto ,  Kimihiko Yamashita

Inventor： Yasunori Hashimoto ,  Kimihiko Yamashita

IPC: H01L29/00

CPC classification number: H01L28/20 ,  H01L27/0611 ,  H01L27/0802

Abstract: A semiconductor device, a method for manufacturing the semiconductor device, and an integrated circuit including the semiconductor device are disclosed. The semiconductor device includes a substrate section, a resistor formed on the substrate section, a metal pattern formed on the resistor, an oxide pattern formed on the metal pattern, and a protective film covering the resistor, the metal pattern and the oxide pattern. With this structure, the metal pattern sufficiently prevents formation of an oxide film on a surface of the resistor even when dry ashing or dry etching is performed in the manufacturing process.

Abstract translation: 公开了半导体器件，半导体器件的制造方法和包括半导体器件的集成电路。 该半导体装置包括基板部，形成在基板部上的电阻，形成在电阻上的金属图案，形成在金属图案上的氧化物图案，以及覆盖电阻，金属图案和氧化物图案的保护膜。 通过这种结构，即使在制造过程中进行干法灰化或干法蚀刻，金属图案也充分地防止了在电阻器的表面上形成氧化膜。

公开(公告)号：US06191466B1

公开(公告)日：2001-02-20

申请号：US09395939

申请日：1999-09-14

Applicant: Yasunori Yamashita ,  Tomohide Terashima ,  Fumitoshi Yamamoto

Inventor： Yasunori Yamashita ,  Tomohide Terashima ,  Fumitoshi Yamamoto

IPC: H01L21336

CPC classification number: H01L27/0611 ,  H01L21/761 ,  H01L29/8611

Abstract: A semiconductor device which has few peripheral element malfunctions and superior performance is obtained. The semiconductor device includes a p-type buried layer on a main surface of a semiconductor substrate, an n-type cathode region provided on the p-type buried layer, and a p-type anode region in contact with the side surface of the n-type cathode region, the p-type buried layer being higher than the p-type anode region in acceptor content, and the p-type buried layer being in contact with the bottom surfaces of the anode and cathode regions.

Abstract translation: 获得了具有极少的外围元件故障和优异性能的半导体器件。 半导体器件包括在半导体衬底的主表面上的p型掩埋层，设置在p型掩埋层上的n型阴极区域和与n型阴极区域接触的p型阳极区域 型阴极区，p型埋层比受体含量高于p型阳极区，p型掩埋层与阳极和阴极区的底表面接触。

公开(公告)号：US5550072A

公开(公告)日：1996-08-27

申请号：US325855

申请日：1994-10-19

Applicant: Philip J. Cacharelis ,  Jeffrey R. Perry ,  Narasimha Narahari

Inventor： Philip J. Cacharelis ,  Jeffrey R. Perry ,  Narasimha Narahari

IPC: H01L21/8247 ,  H01L27/06 ,  H01L27/105 ,  H01L21/82

CPC classification number: H01L27/11526 ,  H01L27/0611 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11551

Abstract: An EEPROM cell is formed in an IC chip by using only three masking steps in addition to those required for the basic CMOS transistors in the chip. A first mask layer is used to define source/drain regions of select and memory transistors within the EEPROM cell; a second mask layer is used to define a tunneling region of the memory transistor;and a third mask layer is used to define a floating gate of the memory transistor and a gate of the select transistor. A control gate of the memory transistor is formed using the same mask that is used to define the gates of the CMOS transistors. The third and fourth mask layers may also be used to form the lower and upper electrodes, respectively, of a capacitor.

Abstract translation: 除了芯片中的基本CMOS晶体管所需的那些之外，仅通过使用三个掩模步骤，在IC芯片中形成EEPROM单元。 第一掩模层用于限定EEPROM单元内的选择和存储晶体管的源极/漏极区域; 第二掩模层用于限定存储晶体管的隧道区;并且第三掩模层用于限定存储晶体管的浮置栅极和选择晶体管的栅极。 使用与用于限定CMOS晶体管的栅极的掩模相同的掩模来形成存储晶体管的控制栅极。 第三和第四掩模层也可以分别用于形成电容器的下电极和上电极。

公开(公告)号：US3639780A

公开(公告)日：1972-02-01

申请号：US3639780D

申请日：1970-06-01

Applicant: GTE SYLVANIA INC

Inventor： LOVELACE RALPH E

IPC: H01L27/06 ,  H04N5/21 ,  H03K5/20

CPC classification number: H04N5/21 ,  H01L27/0611

Abstract: Video signal processing apparatus which amplifies the composite video signal from the video detector of a television receiver and charges a capacitance to the peak voltage of the synchronizing pulses. The composite video signal is compared with the voltage stored in the capacitance by a comparator and an output pulse is produced when the voltage of the composite video signal is high enough to indicate the presence of a synchronizing pulse. The composite video signal is also compared with the stored voltage by a second comparator, and a noise-cancelling signal which prevents noise from affecting the voltage stored on the capacitance of the first comparator is generated when the voltage of the composite video signal is high enough to indicate the presence of noise.

Abstract translation: 视频信号处理装置，放大来自电视接收机的视频检测器的复合视频信号，并将电容充电到同步脉冲的峰值电压。 将复合视频信号与比较器存储在电容中的电压进行比较，并且当复合视频信号的电压足够高以指示存在同步脉冲时产生输出脉冲。 复合视频信号也通过第二比较器与存储的电压进行比较，并且当复合视频信号的电压足够高时，产生防止噪声影响存储在第一比较器的电容上的电压的噪声消除信号 以指示噪声的存在。

公开(公告)号：US3421103A

公开(公告)日：1969-01-07

申请号：US3421103D

申请日：1966-08-02

Applicant: SIEMENS AG

Inventor： NOLDE WOLFGANG

IPC: H01L27/06 ,  H01L27/082 ,  H03F1/34 ,  H03F3/347

CPC classification number: H01L27/082 ,  H01L27/0611 ,  H03F1/34 ,  H03F3/347

公开(公告)号：US09543405B2

公开(公告)日：2017-01-10

申请号：US14228330

申请日：2014-03-28

Applicant: Infineon Technologies AG

Inventor： Holger Ruething ,  Hans-Joachim Schulze ,  Frank Hille ,  Frank Pfirsch

IPC: H01L29/73 ,  H01L29/66 ,  H01L29/32 ,  H01L29/739 ,  H01L27/06 ,  H01L29/167

CPC classification number: H01L29/66348 ,  H01L27/0611 ,  H01L29/167 ,  H01L29/32 ,  H01L29/7397

Abstract: A method of manufacturing a reduced free-charge carrier lifetime semiconductor structure includes forming a plurality of transistor gate structures in trenches arranged in a semiconductor substrate, forming a body region between adjacent ones of the transistor gate structures and forming an end-of-range irradiation region between adjacent ones of the transistor gate structures, the end-of-range irradiation region having a plurality of vacancies.

Abstract translation: 一种制造减小的自由电荷载流子寿命半导体结构的方法包括在布置在半导体衬底中的沟槽中形成多个晶体管栅极结构，在相邻的晶体管栅极结构之间形成体区，并形成距离范围 所述晶体管栅极结构中的相邻晶体管栅极结构之间的区域，所述端部范围照射区域具有多个空位。

公开(公告)号：US20160071798A1

公开(公告)日：2016-03-10

申请号：US14821493

申请日：2015-08-07

Applicant: ROHM CO., LTD.

Inventor： Kunihiro KOMIYA

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/00

CPC classification number: H01L23/5286 ,  H01L23/5226 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/11 ,  H01L25/072 ,  H01L27/0611 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05548 ,  H01L2224/06515 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05099

Abstract: A semiconductor device including a multiplicity of large current power elements with each power element divided into a multiplicity of divisional elements and arranged such that the power elements belonging to different power elements are arranged in a repetitive sequential order. The IC chip of the semiconductor device is formed to have output wires extending from the respective divisional elements connected to corresponding output pads without crossing other output wires. Arranged on the IC chip are output bumps in association with the respective output pads. A rewiring layer is provided having output coupling wires for connecting together the bumps that belong to the same power element and connecting them further to an external output electrode.

Abstract translation: 一种半导体器件，包括多个大电流功率元件，每个功率元件被分成多个分割元件，并且被布置为使得属于不同功率元件的功率元件以重复的顺序排列。 半导体器件的IC芯片形成为具有从连接到对应的输出焊盘的相应分割元件延伸的输出导线，而不会穿过其它输出线。 配置在IC芯片上的是与相应的输出焊盘相关联的输出凸起。 提供了一种重新布线层，其具有用于将属于同一功率元件的凸块连接在一起并将它们进一步连接到外部输出电极的输出耦合线。

公开(公告)号：US09105753B2

公开(公告)日：2015-08-11

申请号：US13957738

申请日：2013-08-02

Applicant: DENSO CORPORATION

Inventor： Masaya Tanaka ,  Hisanori Yokura

IPC: H01L29/82 ,  H01L29/76 ,  H01L21/00 ,  G01L9/06 ,  H01L29/84 ,  G01L9/00 ,  H01L29/8605 ,  H01L27/06

CPC classification number: H01L29/84 ,  G01L9/0042 ,  G01L9/06 ,  H01L27/0611 ,  H01L29/8605

Abstract: A semiconductor physical quantity sensor includes (i) a semiconductor substrate having a first conductive type, (ii) a diaphragm portion disposed in the semiconductor substrate, (iii) a sensing portion disposed in the diaphragm portion, (iv) a well layer having a second conductive type, and (v) a back flow prevention element. The well layer is disposed in a surface portion of the semiconductor substrate, and corresponds to the diaphragm portion. The back flow prevention element is provided by a MOSFET, a JFET, a MESFET, or a HEMT. The back flow prevention element includes two second conductive diffused portions and a gate electrode. The back flow prevention element is arranged on a first electrical wiring, which provides a passage for applying a predetermined voltage to the well layer from an external circuit. The back flow prevention element turns on based on a voltage applied to the gate electrode.

Abstract translation: 半导体物理量传感器包括（i）具有第一导电类型的半导体衬底，（ii）设置在半导体衬底中的隔膜部分，（iii）设置在隔膜部分中的感测部分，（iv）具有 第二导电类型，和（v）防逆流元件。 阱层设置在半导体衬底的表面部分中，并且对应于膜片部分。 背面防流体元件由MOSFET，JFET，MESFET或HEMT提供。 防回流元件包括两个第二导电扩散部分和栅电极。 后防流体元件布置在第一电线上，其提供从外部电路向阱层施加预定电压的通道。 背流防止元件基于施加到栅电极的电压而导通。

公开(公告)号：US20150140746A1

公开(公告)日：2015-05-21

申请号：US14574265

申请日：2014-12-17

Applicant: AVOGY, INC.

Inventor： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano ,  David P. Bour ,  Richard J. Brown ,  Thomas R. Prunty

IPC: H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/66909 ,  H01L21/823487 ,  H01L27/0605 ,  H01L27/0611 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/098 ,  H01L29/2003 ,  H01L29/66143 ,  H01L29/8083 ,  H01L29/872

Abstract: An integrated device including a vertical III-nitride FET and a Schottky diode includes a drain comprising a first III-nitride material, a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, and a channel region comprising a third III-nitride material coupled to the drift region. The integrated device also includes a gate region at least partially surrounding the channel region, a source coupled to the channel region, and a Schottky contact coupled to the drift region. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride FET and the Schottky diode is along the vertical direction.

Abstract translation: 包括垂直III族氮化物FET和肖特基二极管的集成器件包括：包括第一III族氮化物材料的漏极，包括耦合到漏极并沿垂直方向邻近漏极设置的第二III族氮化物材料的漂移区， 以及包括耦合到所述漂移区的第三III族氮化物材料的沟道区。 集成器件还包括至少部分地围绕沟道区的栅极区域，耦合到沟道区的源极和耦合到漂移区域的肖特基接触。 沟道区域沿着垂直方向设置在漏极和源极之间，使得垂直III族氮化物FET和肖特基二极管的工作期间的电流沿垂直方向。

公开(公告)号：US09035425B2

公开(公告)日：2015-05-19

申请号：US13875291

申请日：2013-05-02

Applicant: United Microelectronics Corp.

Inventor： Po-Chao Tsao

IPC: H01L29/00 ,  H01L27/088 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/70

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L27/0611 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/408 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7835 ,  H01L29/7851

Abstract: A semiconductor integrated circuit includes a substrate, a multi-gate transistor device formed on the substrate, and an n-well resistor formed in the substrate. The substrate includes a plurality of first isolation structures and at least a second isolation structure formed therein. A depth of the first isolation structures is smaller than a depth of the second isolation structure. The multi-gate transistor device includes a plurality of fin structures, and the fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The n-well resistor includes at least one first isolation structure. The n-well resistor and the multi-gate transistor device are electrically isolated from each other by the second isolation structure.

Abstract translation: 半导体集成电路包括衬底，形成在衬底上的多栅极晶体管器件和形成在衬底中的n阱电阻器。 衬底包括多个第一隔离结构和至少形成在其中的第二隔离结构。 第一隔离结构的深度小于第二隔离结构的深度。 多栅晶体管器件包括多个翅片结构，并且翅片结构彼此平行并且通过第一隔离结构彼此间隔开。 n阱电阻器包括至少一个第一隔离结构。 n阱电阻器和多栅极晶体管器件通过第二隔离结构彼此电隔离。