中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

172 records (took 0.051 seconds)

    LOCAL INTEGRATION OF NON-LINEAR SHEET I INTEGRATED CIRCUIT PACKAGES FOR ESD/EOS PROTECTION
    11.
    发明申请
    LOCAL INTEGRATION OF NON-LINEAR SHEET I INTEGRATED CIRCUIT PACKAGES FOR ESD/EOS PROTECTION 审中-公开
    非线性片I I集成电路组件ESD / EOS保护的本地集成

    公开(公告)号：US20110075306A1

    公开(公告)日：2011-03-31

    申请号：US12963704

    申请日：2010-12-09

    Applicant: Yves Leduc ,  Nathalie Messina ,  Charvaka Duvvury ,  Kurt P. Wachtler

    Inventor： Yves Leduc ,  Nathalie Messina ,  Charvaka Duvvury ,  Kurt P. Wachtler

    IPC: H02H9/04

    CPC classification number: H01L23/62 ,  H01L23/60 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/13034 ,  H01L2924/15311 ,  H05K1/0259 ,  H05K2201/0738 ,  Y10T29/49105 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

    Abstract: A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.

    Abstract translation: 一种封装半导体器件（200），其具有夹在绝缘体（221）中的基板（220），由预定电压从绝缘体切换到导体模式的非线性材料制成的平板状筛件（240） 。 两个构件表面都没有压痕; 所述构件穿过通孔，所述通孔被分组成第一组（241）和第二组（242）。 一个构件表面上的金属迹线（251）跨过第一组通孔（241）定位; 每个迹线连接到基板顶部上的端子，并且通过孔连接到基板底部上的端子。 类似于相对构件表面上的金属迹线（252）和第二组通孔（242）。 轨迹（252）与轨迹（252）的一部分重叠以形成用于导电开关的位置，从而产生局部超低电阻旁路到地以释放过应力事件。

    System and method for including protective voltage switchable dielectric material in the design or simulation of substrate devices
    13.
    发明授权
    System and method for including protective voltage switchable dielectric material in the design or simulation of substrate devices 有权
    在设计或模拟衬底器件时包括保护电压可切换介电材料的系统和方法

    公开(公告)号：US07793236B2

    公开(公告)日：2010-09-07

    申请号：US11860530

    申请日：2007-09-24

    Applicant: Lex Kosowsky ,  Robert Fleming

    Inventor： Lex Kosowsky ,  Robert Fleming

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  H05K1/0254 ,  H05K1/0259 ,  H05K1/0293 ,  H05K1/0373 ,  H05K3/0005 ,  H05K2201/0738 ,  H05K2203/105

    Abstract: A substrate device is designed by identifying one or more criteria for handling of a transient electrical event on the substrate device. The one or more criteria may be based at least in part on an input provided from a designer. From the one or more criteria, one or more characteristics may be determined for integrating VSD material as a layer within or on at least a portion of the substrate device. The layer of VSD material may be positioned to protect one or more components of the substrate from the transient electrical condition.

    Abstract translation: 通过识别用于处理衬底装置上的瞬态电事件的一个或多个标准来设计衬底装置。 该一个或多个标准可以至少部分地基于从设计者提供的输入。 根据一个或多个标准，可以确定一个或多个特性，用于将VSD材料整合为衬底装置的至少一部分内或之上的层。 可以将VSD材料层定位成保护衬底的一个或多个部件免受瞬态电气条件的影响。

    Metal Deposition
    19.
    发明申请
    Metal Deposition 审中-公开
    金属沉积

    公开(公告)号：US20100038121A1

    公开(公告)日：2010-02-18

    申请号：US12608297

    申请日：2009-10-29

    Applicant: Lex Kosowsky

    Inventor： Lex Kosowsky

    IPC: H05K1/09 ,  C25D5/00 ,  B05D5/12 ,  H05K1/00

    CPC classification number: C25D1/00 ,  C25D1/003 ,  C25D5/022 ,  C25D5/54 ,  H05K1/0254 ,  H05K1/0373 ,  H05K1/167 ,  H05K3/188 ,  H05K3/423 ,  H05K3/426 ,  H05K2201/0215 ,  H05K2201/0738 ,  H05K2203/105

    Abstract: Systems and methods include depositing one or more materials on a voltage switchable dielectric material. In certain aspects, a voltage switchable dielectric material is disposed on a conductive backplane. In some embodiments, a voltage switchable dielectric material includes regions having different characteristic voltages associated with deposition thereon. Some embodiments include masking, and may include the use of a removable contact mask. Certain embodiments include electrografting. Some embodiments include an intermediate layer disposed between two layers.

    Abstract translation: 系统和方法包括在可开关电介质材料上沉积一种或多种材料。 在某些方面，电压可切换介电材料设置在导电背板上。 在一些实施例中，电压可切换介电材料包括具有与其上沉积相关联的不同特征电压的区域。 一些实施例包括掩蔽，并且可以包括使用可移除的接触掩模。 某些实施例包括电驱动。 一些实施例包括设置在两层之间的中间层。

Patent Agency Ranking