-
公开(公告)号：US11894084B2
公开(公告)日：2024-02-06
申请号：US17421483
申请日：2019-02-08
申请人： Intel Corporation
发明人： Dujian Wu , Shijian Ge , Daocheng Bu
CPC分类号： G11C29/10 , G11C29/12005 , G11C29/12015 , G11C29/38 , G11C29/46
摘要： Method, systems and apparatuses may provide for technology that executes a margin test of a first memory storage based on a subset of first signals associated with the first memory storage. The technology determines, based on the margin test, first margin data to indicate whether the first memory storage complies with one or more electrical constraints. The technology determines, based on the first margin data, whether to execute a signal training process.
-
公开(公告)号：US20240013848A1
公开(公告)日：2024-01-11
申请号：US17810671
申请日：2022-07-05
申请人： NXP USA, Inc.
发明人： Kumar Abhishek , Xiankun Jin , Mark Lehmann
摘要： Analog-to-digital converters (ADCs) of an integrated circuit includes a first set of ADCs and second set of ADCs in which the ADCs of the first set are of a different type than the ADCs of the second set. On-chip testing of the ADCs includes calibrating an N-bit differential digital-to-analog converter (DAC) and storing a pair of calibration codes for each of 2N possible DAC input codes for the DAC in an on-chip memory. The first set of ADCs is tested using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC. Subsequently, the second set of ADCs is tested using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, in which M is less than N. During the testing of the second set of ADCs, a portion of the calibration codes stored in the on-chip memory is overwritten.
-
公开(公告)号：US11862279B2
公开(公告)日：2024-01-02
申请号：US17651446
申请日：2022-02-17
发明人： Bo Yang , Xiaodong Luo
CPC分类号： G11C29/789 , G11C7/1069 , G11C7/1096 , G11C29/4401 , G11C29/46
摘要： A method for determining a repaired line and a repairing line in a memory includes the following: writing first preset data sets into respective lines in a normal region, and writing second preset data sets into respective lines in a redundancy region; repairing the lines in the normal region by using the lines in the redundancy region; reading data from the lines in the normal region after repairing; and determining a repaired line in the normal region and a repairing line in the redundancy region according to the data of the lines in the normal region, the data of the lines in the normal region after repairing, or the data of the lines in the redundancy region.
-
公开(公告)号：US11854642B2
公开(公告)日：2023-12-26
申请号：US17310414
申请日：2020-10-15
发明人： Heng-Chia Chang , Li Ding , Chuanqi Shi
CPC分类号： G11C29/46 , G11C29/4401 , G11C29/56004
摘要： A memory test method includes: testing a first memory to acquire defect information of the first memory; acquiring repair information of the first memory according to the defect information of the first memory; and storing the repair information of the first memory in a second memory. In the technical solutions provided in the embodiments of the present disclosure, other memories may be used to store the repair information of the currently tested memory, so that the storage space can be increased and the test efficiency can be improved.
-
公开(公告)号：US20230402123A1
公开(公告)日：2023-12-14
申请号：US18059124
申请日：2022-11-28
发明人： Jaewon Park , Sukhan Lee
CPC分类号： G11C29/46 , G11C29/12005 , G11C29/36 , G11C2029/3602
摘要： Provided is a memory device including a cell array, a peripheral circuit configured to control a memory operation of the plurality of memory cells, a test logic circuit configured to operate in a test mode and configured to perform a test operation on the plurality of memory cells, a first regulator configured to regulate a first power supply voltage received through a first pad and provide the first power supply voltage to at least one of the cell array and the peripheral circuit, and a power manager between the first pad and an input terminal of the first regulator, and between the first pad and the test logic circuit and configured to provide a test power supply voltage to the test logic circuit. In the test mode, while a first target voltage level of the first regulator fluctuates, a second target voltage level of the power manager is maintained constant.
-
公开(公告)号：US11791012B2
公开(公告)日：2023-10-17
申请号：US17515776
申请日：2021-11-01
发明人： Yui-Lang Chen
CPC分类号： G11C29/46 , G11C29/10 , G11C29/4401 , G11C29/785 , G11C2029/1202
摘要： Provided are standby circuit dispatch method, apparatus, device and medium. The method includes: a first test item is executed and first test data is acquired, the first test data including position data of a failure bit acquired during execution of the first test item; a first redundant circuit dispatch result is determined according to the first test data; a second test item is executed and second test data is acquired; when the failure bit acquired during execution of the second test item includes a failure bit outside the repair range of the dispatched regional redundant circuits and dispatched global redundant circuits, and the dispatchable redundant circuits have been dispatched out, a maximum target bit umber is acquired according to the first test data and the second test data; and a target dispatch mode is selected and a second redundant circuit dispatch result is determined according to the target dispatch mode.
-
公开(公告)号：US20230317198A1
公开(公告)日：2023-10-05
申请号：US17898992
申请日：2022-08-30
发明人： Jong Sun PARK , Kwan Ho BAE , Jin Ho JEONG , Seung Hwan BANG
CPC分类号： G11C29/46 , G11C29/785 , G11C29/4401
摘要： A dynamic fault clustering method and apparatus for efficiently managing redundancy in semiconductor memories performs a collection operation of searching for and detecting a fault and an operation of appropriately clustering the fault at the same time, which reduces an amount of time spent performing Built-In Redundancy Analysis (BIRA).
-
公开(公告)号：US11710534B1
公开(公告)日：2023-07-25
申请号：US17682837
申请日：2022-02-28
发明人： Christian N. Mohr , Scott E. Smith , Manoj Vijay
CPC分类号： G11C29/52 , G11C29/021 , G11C29/12005 , G11C29/38 , G11C29/46 , G11C29/787 , G11C2029/0409
摘要： Embodiments presented herein are directed to testing and/or debugging a memory device of a memory module (e.g., a dual in-line memory module (DIMM)) without having to remove the DIMM from a corresponding computing device and without having to interrupt operation of the computing device. A particular memory device (e.g., DRAM) may be identified for testing and/or debugging based on a failure message. However, the failure message may not identify a specific location or hardware of the module that caused the failure. Embodiments presented herein provide techniques to obtain data for analysis to determine and/or deliver a cause of the failure while reducing or eliminating downtime of the computing device. Test modes to do so may include a synchronous test mode, an asynchronous test mode, and an analog compare mode. A test mode may be selected based on the failure or a signal/function of the DRAM to be tested or debugged.
-
公开(公告)号：US20230230649A1
公开(公告)日：2023-07-20
申请号：US17808701
申请日：2022-06-24
发明人： Dong LIU
CPC分类号： G11C29/1201 , G11C7/1048 , G11C29/46 , G11C29/12015
摘要： A method for testing a memory chip includes the following: test data is written into memory cells of a memory chip to be tested; stored data is read from memory cells; a test result of the memory chip to be tested is generated according to the test data and the stored data. A current voltage of bit line precharge (VBLP) of the memory chip to be tested is smaller than a standard VBLP of the memory chip to be tested, and/or a current sensing delay time (SDT) of the memory chip to be tested is smaller than a standard SDT of the memory chip to be tested.
-
公开(公告)号：US20230223096A1
公开(公告)日：2023-07-13
申请号：US18122038
申请日：2023-03-15
申请人： Intel Corporation
CPC分类号： G11C29/42 , G11C29/46 , G11C29/1201
摘要： Methods and apparatus for configurable ECC (error correction code) mode in DRAM. Selected memory cells in the bank arrays of a DRAM device (e.g., die) are used to store ECC bits. A DRAM device (e.g., die) is configured to operate in a first mode in which an on-die ECC engine employs selected bits in the arrays of memory cells in the DRAM banks as ECC bits to perform ECC operations and to operate in a second mode under which the ECC bits are not employed for ECC operations by the ECC engine and made available for external use by a host. In the second mode, the repurposed ECC bits may comprise RAS bits used for RAS (Reliability, Serviceability, and Availability) operations and/or metabits comprising metadata used for other operations by the host.
-
-
-
-
-
-
-
-
-
搜索结果
535 条记录 (耗时 0.026 秒)
