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11.发明授权公开(公告)号：US06954159B1
公开(公告)日：2005-10-11
申请号：US10612829
申请日：2003-07-01
摘要： A low-distortion band-pass delta-sigma analog-to-digital converter (ADC), including an odd-phase sample and hold circuit coupled to a even-phase resonator, improves tolerance to mismatches between analog circuit components. The low-distortion ADC includes a feed-forward signal path that reduces, or eliminates, the input signal beyond the first summation point. In this way, the dynamic range and matching accuracy required of the resonator is reduced. An odd-phase sample and hold circuit shifts S/H spurious signals out-of-band. A two-phase resonator reduces in-band noise degradation caused by any mismatches between the resonator components.
摘要翻译： 低失真带通delta-sigma模数转换器（ADC），包括耦合到偶相谐振器的奇数相位采样和保持电路，提高了模拟电路组件之间的失配容限。 低失真ADC包括前馈信号路径，其减少或消除超出第一求和点的输入信号。 以这种方式，减小了谐振器所需的动态范围和匹配精度。 奇数相位采样和保持电路将S / H杂散信号移出带外。 两相谐振器减少由谐振器部件之间的任何失配引起的带内噪声劣化。
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公开(公告)号：US06952174B2
公开(公告)日：2005-10-04
申请号：US10237992
申请日：2002-09-09
CPC分类号： H04S1/007
摘要： A method of encoding a first stream of digital signal data words is provided. A most recent value of the first stream of digital signal data words is received and memorized. A previous value of the first stream of digital data words is received and memorized. The most recent and the previous values of the stream of digital data words are combined to create a second data stream. The words are converted in the second data stream into a serial representation. The serial representation is transmitted on a single wire interface.
摘要翻译： 提供了一种对第一数字信号数据字进行编码的方法。 数字信号数据字的第一个流的最新值被接收和记忆。 数字数据字的第一个流的先前值被接收和存储。 数字数据流流的最新值和先前值被组合以产生第二数据流。 这些词在第二数据流中被转换为串行表示。 串行表示在单线接口上传输。
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公开(公告)号：US06937176B2
公开(公告)日：2005-08-30
申请号：US10950760
申请日：2004-09-27
申请人： Steven R. Freeman , Gary Allen Schwartz , Raf Lodewijk Jan Roovers , Lucien Johannes Breems , George Anthony Brock-Fisher , Theodore Philip Fazioli
发明人： Steven R. Freeman , Gary Allen Schwartz , Raf Lodewijk Jan Roovers , Lucien Johannes Breems , George Anthony Brock-Fisher , Theodore Philip Fazioli
CPC分类号： G01S7/52028 , G01S7/52095 , G01S15/8979 , H03M3/43 , H03M3/46
摘要： A receive beamformer, and ultrasound system incorporating such a receive beamformer, is constructed to implement multi-bit analog to digital conversion in such a way that the need for gain control in the channel architecture preceding the digital conversion circuitry is obviated. Accordingly, the beamformer and any ultrasound system incorporating it may realize a rigorous level of ADC performance at desirable output rates, and a lower cost. Preferably, the invention construction realizes a level of performance by which CW Doppler may be digitized in the same manner as very wide-band pulsed-wave signals.
摘要翻译： 构造接收波束形成器和结合这样的接收波束形成器的超声系统，以便实现多比特模数转换，从而避免在数字转换电路之前的信道架构中增益控制的需要。 因此，波束形成器和其中包含的任何超声波系统可以以期望的输出速率实现严格的ADC性能水平，并且降低成本。 优选地，本发明的结构实现了与多普勒脉冲波信号相同的方式，CW多普勒可以被数字化的性能水平。
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公开(公告)号：US06914549B2
公开(公告)日：2005-07-05
申请号：US10661861
申请日：2003-09-12
申请人： Feng Chen , Ranjit Gharpurey
发明人： Feng Chen , Ranjit Gharpurey
摘要： Configuring an analog-to-digital converter includes receiving a control signal and an input analog signal at an analog-to-digital converter, where the control signal has either a first state or a second state. The first state is associated with a first configuration and the second state is associated with a second configuration. If the control signal has the first state, the analog-to-digital-converter is configured in the first configuration and a digital signal comprising a first digital signal is generated according to a pipeline conversion. If the control signal has the second state the analog-to-digital converter is configured in the second configuration and the digital signal comprising a second digital signal is generated according to a multi-stage sigma delta modulation conversion. The digital signal is processed to yield a digital output.
摘要翻译： 配置模数转换器包括在模拟 - 数字转换器处接收控制信号和输入模拟信号，其中控制信号具有第一状态或第二状态。 第一状态与第一配置相关联，并且第二状态与第二配置相关联。 如果控制信号具有第一状态，则在第一配置中配置模数转换器，并且根据流水线转换产生包括第一数字信号的数字信号。 如果控制信号具有第二状态，则在第二配置中配置模数转换器，并且根据多级Σ-Δ调制转换产生包括第二数字信号的数字信号。 数字信号被处理以产生数字输出。
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15.发明申请Hardware-efficient implementation of dynamic element matching in sigma-delta DAC's 失效在Σ-ΔDAC中实现动态元件匹配的高效实现公开(公告)号：US20050134492A1
公开(公告)日：2005-06-23
申请号：US11028568
申请日：2005-01-05
申请人： Minsheng Wang , Anil Tammineedi
发明人： Minsheng Wang , Anil Tammineedi
CPC分类号： G06F7/762 , H03M1/0665 , H03M3/338 , H03M3/464 , H03M3/502
摘要： A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0′, x1′} such that a number of 1's at bit x0′ over time is within ∀1 of a number of 1's at bit x1′. At least two 4-bit vector shufflers input the vectors {x0′, x1′}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0′, x1′} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0′, x1′} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.
摘要翻译： 用于混洗输入比特的数据洗牌器装置包括多个比特洗牌器，每个比特混洗器输入相应的输入比特的两个比特x 0和x 1，并且输出向量{x 0 '，x <1>，使得在位x 0处的1的数量在时间上处于位1的1的位置之内 1＆lt; 1＆gt;。 至少两个4位向量混洗器输入向量{x <0> 0
>，x 1> 1，并输出4位向量，每个4位向量对应于 由比特洗牌器产生的对应的两个向量{x <0>，x 1“}的组合，使得4比特向量混洗器对向量{x 0 >，x 1> 。 基于4位向量洗牌器的下一个状态来更新位洗牌器的当前状态。 -
公开(公告)号：US20050128111A1
公开(公告)日：2005-06-16
申请号：US11047750
申请日：2005-02-02
申请人： Todd Brooks
发明人： Todd Brooks
CPC分类号： H03M1/0641 , H03M1/74 , H03M3/332 , H03M3/424
摘要： Methods and systems for applying digital dither in data converters, such as delta-sigma data converters. In one embodiment, an analog signal from a first path of a delta-sigma modulator is quantized to an m-bit digital signal and an n-bit dithered digital feedback signal is generated from at least a portion of the m-bit digital signal. The n-bit dithered digital feedback signal is converted to an analog feedback signal and fed back to a second path of the delta-sigma modulator. In another embodiment, the n-bit dithered digital feedback signal is generated by selecting one of a plurality of sets of n-bits from the m-bit digital signal depending upon a state of a dither control signal. The dither control signal can alternate or pseudo-randomly switch between a plurality of states. The m-bit digital signal may be an m-bit thermometer code signal.
摘要翻译： 在数据转换器中应用数字抖动的方法和系统，如delta-sigma数据转换器。 在一个实施例中，来自Δ-Σ调制器的第一路径的模拟信号被量化为m位数字信号，并且从m位数字信号的至少一部分产生n位抖动数字反馈信号。 n位抖动数字反馈信号被转换成模拟反馈信号并反馈到Δ-Σ调制器的第二路径。 在另一个实施例中，根据抖动控制信号的状态，通过从m位数字信号中选择多个n位组中的一个产生n位抖动数字反馈信号。 抖动控制信号可以在多个状态之间交替或伪随机切换。 m位数字信号可以是m位温度计代码信号。
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17.发明申请Analog signal outputting circuit and multi-level delta-sigma modulator employing the analog signal outputting circuit 有权模拟信号输出电路和采用模拟信号输出电路的多级Δ-Σ调制器公开(公告)号：US20050078023A1
公开(公告)日：2005-04-14
申请号：US10948654
申请日：2004-09-24
申请人： Tetsuya Matsumoto
发明人： Tetsuya Matsumoto
CPC分类号： H03M3/344 , H03M3/358 , H03M3/502 , H03M7/3026 , H03M7/3031
摘要： An analog signal outputting circuit comprises two unit analog circuits for outputting an analog signal, corresponding to levels “−1” or “1”, and a low-pass filter for smoothing the analog signal output from the two unit analog circuits, as selected by codes output from the four-valued delta-sigma modulator. In case the input signal is −2 or +2, outputs of the unit analog circuits are summed together to output an analog signal corresponding to −2 or +2. In case the input signal is −1 or +1, outputs of the unit analog circuits are alternately used to output an analog signal corresponding to −1 or +1 to reduce the non-linearity error resulting from variations in the analog devices.
摘要翻译： 模拟信号输出电路包括两个单元模拟电路，用于输出对应于电平“-1”或“1”的模拟信号，以及低通滤波器，用于平滑从两个单元模拟电路输出的模拟信号，如由 从四值Δ-Σ调制器输出的代码。 在输入信号为-2或+2的情况下，将单位模拟电路的输出相加在一起，输出对应于-2或+2的模拟信号。 在输入信号为-1或+1的情况下，单位模拟电路的输出交替用于输出对应于-1或+1的模拟信号，以减少由模拟装置的变化引起的非线性误差。
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公开(公告)号：US06853325B2
公开(公告)日：2005-02-08
申请号：US10740754
申请日：2003-12-22
申请人： Masako Arizumi , Hiroyuki Harada
发明人： Masako Arizumi , Hiroyuki Harada
CPC分类号： H03F3/217 , H03M1/0872 , H03M1/822 , H03M3/376 , H03M3/506
摘要： In a digital amplifier, a time controller generates first and second selection signals for outputting any one of music data, a center output, and a lowest output to a P output and an N output based on a power ON/OFF signal and a start/stop signal, and also generates a third selection signal for determining whether a signal having the same phase as that of the P output is output to the N output or a signal obtained by inverting the P output is output to the N output. A data selection circuit determines data to be output to the P output and the N output based on the first and second selection signals. An output data register circuit converts parallel data determined by the data selection circuit into serial data to output the serial data into the P output. An output selection circuit determines the N output based on the third selection signal.
摘要翻译： 在数字放大器中，时间控制器产生用于将音频数据，中心输出和最低输出中的任何一个输出到P输出和N输出的第一和第二选择信号，其基于电源ON / OFF信号和开始/ 并且还产生用于确定与P输出具有相同相位的信号是否被输出到N输出的第三选择信号或者通过将P输出反相获得的信号被输出到N输出。 数据选择电路基于第一和第二选择信号确定要输出到P输出和N输出的数据。 输出数据寄存器电路将由数据选择电路确定的并行数据转换成串行数据，将串行数据输出到P输出。 输出选择电路根据第三选择信号确定N输出。
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19.发明授权Signal processing system with baseband noise modulation and noise fold back reduction 有权信号处理系统，具有基带噪声调制和噪声折回公开(公告)号：US06842486B2
公开(公告)日：2005-01-11
申请号：US10425285
申请日：2003-04-29
CPC分类号： H03M3/34 , H03F1/02 , H03F1/26 , H03F3/211 , H03F3/217 , H03F3/2175 , H03F3/38 , H03F2200/331 , H03M3/50
摘要： A digital-to-analog converter (“DAC”) system utilizes chopping modulation technology to remove 1/f and other baseband noise from a baseband of a signal of interest. Chopping modulation and demodulation circuitry of the DAC operate at a chopping frequency equal to approximately one-half of a digital input signal sampling frequency. Chopping at one-half the sampling frequency allows fold back into the baseband of the input signal's frequency components and reduces fold back of noise, such as quantization noise, residing outside the baseband. In a further embodiment, a notch filter attenuates signals having frequencies around the chopping frequency prior to chopping to reduce fold back of noise into the baseband due to parasitic modulation. Coordination of chopping timing also reduces noises in the output of the DAC system.
摘要翻译： 数模转换器（“DAC”）系统利用斩波调制技术从感兴趣信号的基带去除1 / f和其他基带噪声。 DAC的斩波调制和解调电路以等于数字输入信号采样频率的大约一半的斩波频率工作。 以采样频率的一半斩波允许折回到输入信号的频率分量的基带，并减少驻留在基带外的诸如量化噪声的噪声的折返。 在另一实施例中，陷波滤波器在斩波之前衰减具有围绕斩波频率的频率的信号，以减少由于寄生调制而导致的基带的噪声折回。 斩波定时的协调还可以减少DAC系统输出的噪声。
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公开(公告)号：US6031481A
公开(公告)日：2000-02-29
申请号：US83277
申请日：1998-05-22
申请人： Peter Graham Craven
发明人： Peter Graham Craven
CPC分类号： H03M1/1038 , H03M1/208 , H03M3/506 , H03M1/504 , H03M1/822
摘要： A signal convertor comprising a pulse modulator. and means for modifying the signal input thereto in dependence upon the error in previous values or the output thereof, to reduce the effects of said error within a desired signal band.
摘要翻译： 一种包括脉冲调制器的信号转换器。 以及用于根据先前值或其输出中的误差修改输入到其中的信号的装置，以减少所需信号频带内的所述误差的影响。
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