公开(公告)号：US20190265406A1

公开(公告)日：2019-08-29

申请号：US15905165

申请日：2018-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli

IPC: G02B6/122 ,  G02B6/13 ,  G02B6/132 ,  G02B6/136

Abstract: Waveguide structures and methods of fabricating waveguide structures. A first airgap is formed in a bulk semiconductor substrate, and a semiconductor layer is epitaxially grown over the bulk semiconductor substrate and the first airgap. First and second trench isolation regions extend through the semiconductor layer and into the bulk semiconductor substrate, and are spaced to define a waveguide core region including a section of the bulk semiconductor substrate and a section of the semiconductor layer that are arranged between the first and second trench isolation regions. A dielectric layer is formed over the waveguide core region, and a second airgap is formed in the dielectric layer. The first airgap is arranged in the bulk semiconductor substrate between the first trench isolation region and the second trench isolation region and under the waveguide core region. The second airgap in the dielectric layer is arranged over the waveguide core region.

公开(公告)号：US10396026B2

公开(公告)日：2019-08-27

申请号：US14990653

申请日：2016-01-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/528 ,  H01L23/532

Abstract: Embodiments of the present invention provide a method for cuts of sacrificial metal lines in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. A line cut lithography stack is deposited and patterned over the sacrificial Mx+1 lines and a cut cavity is formed. The cut cavity is filled with dielectric material. A selective etch process removes the sacrificial Mx+1 lines, preserving the dielectric that fills in the cut cavity. Precut metal lines are then formed by depositing metal where the sacrificial Mx+1 lines were removed. Thus embodiments of the present invention provide precut metal lines, and do not require metal cutting. By avoiding the need for metal cutting, the risks associated with metal cutting are avoided.

公开(公告)号：US10395981B2

公开(公告)日：2019-08-27

申请号：US15793253

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Jeremy Austin Wahl

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L29/04

Abstract: The present disclosure relates to semiconductor devices and manufacturing techniques in which topography-related contact failures may be reduced by providing a dielectric fill material in a late manufacturing stage. In sophisticated semiconductor devices, the material loss in the trench isolation regions may result in significant contact failures, which may be reduced by levelling the device topography, thereby tolerating a significant lateral overlap of contact elements with trench isolation regions.

公开(公告)号：US10395980B1

公开(公告)日：2019-08-27

申请号：US15901411

申请日：2018-02-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Motoi Ichihashi ,  Atsushi Ogino

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines.

公开(公告)号：US10395926B1

公开(公告)日：2019-08-27

申请号：US15954736

申请日：2018-04-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Minghao Tang ,  Yuping Ren ,  Sean Xuan Lin ,  Shao Beng Law ,  Genevieve Beique ,  Xun Xiang ,  Rui Chen

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

Abstract: Methods of self-aligned multiple patterning. A mandrel line is formed over a hardmask layer, and forming a block mask is formed over a first portion of the mandrel line that is linearly arranged between respective second portions of the mandrel line. After forming the first block mask, the second portions of the mandrel line are removed with an etching process to cut the mandrel line and expose respective portions of the hardmask layer. A second portion of the mandrel line is covered by the block mask during the etching process to define a mandrel cut in the mandrel line.

公开(公告)号：US10395752B2

公开(公告)日：2019-08-27

申请号：US15730078

申请日：2017-10-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： John A. Fifield ,  Eric D. Hunt-Schroeder ,  Darren L. Anand

IPC: G11C16/04 ,  G11C29/50 ,  H01L27/11517

Abstract: The present disclosure relates to a structure which includes a twin-cell memory which includes a first device and a second device and which is configured to store data which corresponds to a threshold voltage difference between the first device controlled by a first wordline and the second device controlled by a second wordline.

公开(公告)号：US20190259667A1

公开(公告)日：2019-08-22

申请号：US15898569

申请日：2018-02-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Ruilong XIE

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/08

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions; contacts connecting to the source and drain regions; contacts connecting to the gate structures which are offset from the contacts connecting to the source and drain regions; and interconnect structures in electrical contact with the contacts of the gate structures and the contacts of the source and drain regions.

公开(公告)号：US10388731B2

公开(公告)日：2019-08-20

申请号：US15925051

申请日：2018-03-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: B82Y10/00 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L27/092 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/8238

Abstract: A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

公开(公告)号：US10388617B2

公开(公告)日：2019-08-20

申请号：US15793130

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Ronald Gene Filippi, Jr.

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/308 ,  H01L21/60

Abstract: The present disclosure relates generally to flip chip technology and more particularly, to a method for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure and a structure formed thereby. In an embodiment, a method is disclosed that includes forming a C4 pad on a patterned dielectric layer having grooves therein, the grooves providing an interfacial surface area between the patterned dielectric layer and the C4 pad sufficient to inhibit the C4 pad from delaminating during thermal expansion or contraction.

公开(公告)号：US10381442B2

公开(公告)日：2019-08-13

申请号：US15954300

申请日：2018-04-16

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Chun-chen Yeh

IPC: H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/417 ,  H01L21/324 ,  H01L21/02 ,  H01L21/265 ,  H01L29/45 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8238

Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.