公开(公告)号：US11698725B2

公开(公告)日：2023-07-11

申请号：US17452468

申请日：2021-10-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Toru Tanzawa

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G11C16/26 ,  G11C16/30 ,  G11C8/12 ,  G11C11/56 ,  G11C16/08 ,  G11C13/00 ,  G11C16/04

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/16 ,  G06F13/42 ,  G11C8/12 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0038 ,  G11C16/0483 ,  G11C2207/2209

Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

公开(公告)号：US20220155958A1

公开(公告)日：2022-05-19

申请号：US17452468

申请日：2021-10-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Toru Tanzawa

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G11C16/26 ,  G11C16/30 ,  G11C8/12 ,  G11C11/56 ,  G11C16/08

Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

公开(公告)号：US11145673B2

公开(公告)日：2021-10-12

申请号：US16806755

申请日：2020-03-02

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  G11C8/10 ,  H01L21/02 ,  H01L27/11529 ,  H01L29/49

Abstract: Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.

公开(公告)号：US11018135B2

公开(公告)日：2021-05-25

申请号：US16890673

申请日：2020-06-02

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/108 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11578 ,  H01L21/74 ,  H01L27/02 ,  H01L27/11

Abstract: Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.

公开(公告)号：US20210020214A1

公开(公告)日：2021-01-21

申请号：US16983604

申请日：2020-08-03

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C8/10 ,  G11C7/02 ,  G11C8/12 ,  G11C8/16 ,  G11C8/18 ,  G11C5/02 ,  G11C5/06 ,  G11C11/408 ,  G11C7/00 ,  G11C13/00

Abstract: Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.

公开(公告)号：US20210020204A1

公开(公告)日：2021-01-21

申请号：US16921206

申请日：2020-07-06

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C5/06 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11529 ,  G11C16/26 ,  G11C5/02 ,  G11C7/12 ,  G11C7/22

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

公开(公告)号：US10796778B2

公开(公告)日：2020-10-06

申请号：US16694043

申请日：2019-11-25

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/34 ,  G11C16/06 ,  G11C16/08 ,  G11C16/04 ,  G11C16/32 ,  G11C16/26 ,  G11C16/16 ,  G11C8/08

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

公开(公告)号：US20200265895A1

公开(公告)日：2020-08-20

申请号：US16868777

申请日：2020-05-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa ,  Han Zhao

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/08

Abstract: Methods of operating a memory include activating a respective memory cell of each string of series-connected memory cells of a plurality of strings of series-connected memory cells, selectively activating a target memory cell of a selected string of series-connected memory cells of the plurality of strings of series-connected memory cells depending upon its data state, and deactivating a respective memory cell of each string of series-connected memory cells of a first subset of the plurality of strings of series-connected memory cells.

公开(公告)号：US10748918B2

公开(公告)日：2020-08-18

申请号：US15875407

申请日：2018-01-19

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor device structure comprises stacked tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and an opening laterally adjacent a first side of the at least one staircase structure and extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. Conductive structures of the stacked tiers laterally extend from the steps of the at least one staircase structure completely across a second side of the at least one staircase structure opposing the first side to form continuous conductive paths laterally extending completely across the stacked tiers. Additional semiconductor device structures, methods of forming semiconductor device structures, and electronic systems are also described.

公开(公告)号：US10741259B2

公开(公告)日：2020-08-11

申请号：US16366201

申请日：2019-03-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa ,  Aaron Yip

IPC: G11C16/04 ,  G11C16/28 ,  G11C7/02 ,  G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24

Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.