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    Apparatuses and methods of reading memory cells based on response to a test pulse
    194.
    发明授权
    Apparatuses and methods of reading memory cells based on response to a test pulse 有权
    基于对测试脉冲的响应来读取存储器单元的装置和方法

    公开(公告)号：US09275730B2

    公开(公告)日：2016-03-01

    申请号：US14251002

    申请日：2014-04-11

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0045 ,  G11C2013/0057

    Abstract: The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. The method additionally comprises determining whether a threshold voltage (Vth) of the memory cell has a value within a predetermined read voltage window. A test pulse is applied to the memory cell if it is determined that the threshold voltage has a value within the predetermined read voltage window. The state of the memory cell may be determined based on a response of the memory cell to the test pulse, wherein the state corresponds to the one of the pluralities of states of the memory cell prior to receiving the test pulse.

    Abstract translation: 所公开的技术通常涉及其操作的存储装置和方法，更具体地涉及读取存储器阵列（诸如交叉点存储器阵列）中的存储器单元的存储器阵列和方法。 在一个方面，所述方法包括提供包括以多种状态之一的存储器单元的存储器阵列。 该方法还包括确定存储器单元的阈值电压（Vth）是否具有在预定读取电压窗口内的值。 如果确定阈值电压具有预定读取电压窗口内的值，则将测试脉冲施加到存储器单元。 可以基于存储器单元对测试脉冲的响应来确定存储器单元的状态，其中该状态在接收测试脉冲之前对应于存储单元的多个状态中的一个状态。

    Asymmetric memory cell design
    196.
    发明授权
    Asymmetric memory cell design 有权

    公开(公告)号：US12295147B2

    公开(公告)日：2025-05-06

    申请号：US17818923

    申请日：2022-08-10

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Robustelli ,  Innocenzo Tortorelli

    IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

    Abstract: Methods, systems, and devices for asymmetric memory cell design are described. A memory device may implement a programming scheme that uses low programming pulses based on an asymmetric memory cell design. For example, the asymmetric memory cells may have electrodes with different contact areas (e.g., widths) and may accordingly be biased to a desired polarity (e.g., negative biased or positive biased) for programming operations. That is, the asymmetric memory cell design may enable an asymmetric read window budget. For example, an asymmetric memory cell may be polarity biased, supporting programming operations for logic states based on the polarity bias.

    Techniques for forming self-aligned memory structures
    197.
    发明授权
    Techniques for forming self-aligned memory structures 有权

    公开(公告)号：US12219883B2

    公开(公告)日：2025-02-04

    申请号：US17881274

    申请日：2022-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Stephen W. Russell ,  Andrea Redaelli ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Lorenzo Fratin

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.

    REFERENCING MEMORY USING PORTIONS OF A SPLIT LOGICAL BLOCK ADDRESS
    198.
    发明申请
    REFERENCING MEMORY USING PORTIONS OF A SPLIT LOGICAL BLOCK ADDRESS 有权

    公开(公告)号：US20240427699A1

    公开(公告)日：2024-12-26

    申请号：US18747037

    申请日：2024-06-18

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Robustelli ,  Innocenzo Tortorelli ,  Alessandro Novati ,  Nicola Colella ,  Antonino Pollio

    IPC: G06F12/02 ,  G06F13/16

    Abstract: The subject application related to referencing memory using portions of a split logical block address. A method includes receiving a memory operation including a logical block address (LBA). The method also includes splitting the LBA into a first portion and a second portion. The method further includes determining a physical block of a memory using a logical-to-physical (L2P) table to map the first portion of the LBA to the physical block. The physical block includes a plurality of physical block addresses (PBAs). The method further includes combining the second portion of the LBA and the physical block to reference a physical block address (PBA) of the physical block. The method further includes performing the memory operation at the PBA of the physical block.

    Operating a chalcogenide memory with vertical word and vertical word switching elements
    199.
    发明授权
    Operating a chalcogenide memory with vertical word and vertical word switching elements 有权

    公开(公告)号：US12176042B2

    公开(公告)日：2024-12-24

    申请号：US17651218

    申请日：2022-02-15

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Innocenzo Tortorelli

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

    Abstract: Methods, systems, and devices for techniques for operating a vertical memory architecture are described. A memory device may include memory cells arranged in a three-dimensional vertical memory architecture. Each memory cell may include a storage element (e.g., a chalcogenide material), where a logic state may be programmed at the storage element based on a polarity of an applied voltage that exceeds a threshold voltage. The storage element may be coupled with a selection element and a conductive line. The selection element may be coupled with a bit line decoder and a word line decoder via vertical pillars. The selection element may selectively couple the storage element with the bit line decoder. In some examples, an activation voltage for the selection element may be less than a threshold voltage of the storage element.

    TECHNIQUES FOR MULTI-LEVEL MEMORY CELL PROGRAMMING
    200.
    发明申请
    TECHNIQUES FOR MULTI-LEVEL MEMORY CELL PROGRAMMING 有权

    公开(公告)号：US20240404590A1

    公开(公告)日：2024-12-05

    申请号：US18742753

    申请日：2024-06-13

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Alessandro Sebastiani ,  Mattia Robustelli ,  Matteo Impalà

    IPC: G11C11/56 ,  G11C13/00

    Abstract: Methods, systems, and devices for improved techniques for multi-level memory cell programming are described. A memory array may receive a first command to store a first logic state in a memory cell for storing three or more logic states. The memory array may apply, as part of an erase operation, a first pulse with a first polarity to a plurality of memory cells to store a second logic state different from the first logic state in the plurality of memory cells, where the plurality of memory cells includes the memory cell. The memory array may apply, as part of a write operation or as part of the erase operation, one or more second pulses with a second polarity to the memory cell to store the first logic state in the memory cell based on applying the first pulse.

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