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    Integrated cantilever switch
    191.
    发明授权
    Integrated cantilever switch 有权

    公开(公告)号：US10861984B2

    公开(公告)日：2020-12-08

    申请号：US16564860

    申请日：2019-09-09

    Applicant: STMicroelectronics, Inc.

    Inventor： Qing Liu ,  John H. Zhang

    IPC: H01L29/84 ,  H01H59/00 ,  H01H1/00 ,  B82B3/00 ,  H01H49/00 ,  H01L21/02 ,  H01L21/306 ,  H01H50/00

    Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

    DUAL WIDTH FINFET
    195.
    发明申请
    DUAL WIDTH FINFET 审中-公开

    公开(公告)号：US20180076306A1

    公开(公告)日：2018-03-15

    申请号：US15806160

    申请日：2017-11-07

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Qing Liu

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66818 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/785

    Abstract: A dual width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabrication of such a dual width FinFET entails laterally recessing the strained fin in the source and drain regions using a wet chemical etching process so as to maintain a high degree of strain in the fin while trimming the widths of fin portions in the source and drain regions to less than 5 nm. The resulting FinFET features a wide portion of the fin in the channel region underneath the gate, and a narrower portion of the fin in the source and drain regions. An advantage of the narrower fin is that it can be more easily doped during the growth of the epitaxial raised source and drain regions.

    FinFET having a non-uniform fin
    196.
    发明授权
    FinFET having a non-uniform fin 有权

    公开(公告)号：US09865710B2

    公开(公告)日：2018-01-09

    申请号：US14843221

    申请日：2015-09-02

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Qing Liu

    IPC: H01L21/306 ,  H01L21/78 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66818 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/785

    Abstract: A dual width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabrication of such a dual width FinFET entails laterally recessing the strained fin in the source and drain regions using a wet chemical etching process so as to maintain a high degree of strain in the fin while trimming the widths of fin portions in the source and drain regions to less than 5 nm. The resulting FinFET features a wide portion of the fin in the channel region underneath the gate, and a narrower portion of the fin in the source and drain regions. An advantage of the narrower fin is that it can be more easily doped during the growth of the epitaxial raised source and drain regions.

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