中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

361 records (took 0.03 seconds)

    High Density Split-Gate Memory Cell
    192.
    发明申请
    High Density Split-Gate Memory Cell 审中-公开
    高密度分离栅极存储单元

    公开(公告)号：US20160217849A1

    公开(公告)日：2016-07-28

    申请号：US15002302

    申请日：2016-01-20

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Xian Liu ,  Vipin Tiwari ,  Hieu Van Tran

    IPC: G11C11/419 ,  G11C16/14 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788

    CPC classification number: G11C11/419 ,  G11C16/0458 ,  G11C16/14 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7887

    Abstract: A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.

    Abstract translation: 一种形成存储器件的方法，包括在衬底上形成第一绝缘层，第一导电层，第二绝缘层，第二导电层，第三绝缘层。 第一沟槽通过第三绝缘层，第二导电层，第二绝缘层和第一导电层形成，从而使第一导电层的侧面部分露出。 第一绝缘层形成在沿第一导电层的暴露部分延伸的第一沟槽的底部。 第一个沟槽填充有导电材料。 第二沟槽通过第三绝缘层，第二导电层，第二绝缘层和第一导电层形成。 在第二沟槽下的衬底中形成漏区。 导致一对存储单元，其中单个连续沟道区域在用于该对存储单元的漏极区域之间延伸。

    Method Of Making Embedded Memory Device With Silicon-On-Insulator Substrate
    195.
    发明申请
    Method Of Making Embedded Memory Device With Silicon-On-Insulator Substrate 有权
    使用绝缘体上硅衬底制造嵌入式存储器件的方法

    公开(公告)号：US20160086962A1

    公开(公告)日：2016-03-24

    申请号：US14491596

    申请日：2014-09-19

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chien-Sheng Su ,  Hieu Van Tran ,  Mandana Tadayoni ,  Nhan Do ,  Jeng-Wei Yang

    IPC: H01L27/115 ,  H01L21/762 ,  H01L29/423 ,  H01L21/306 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/7624 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/66825

    Abstract: A method of forming a semiconductor device starts with a substrate of silicon, a first insulation layer on the silicon, and a silicon layer on the first insulation layer. The silicon layer and the insulation layer are removed just from a second substrate area. A second insulation layer is formed over the silicon layer in the substrate first area and over the silicon in the second substrate area. A first plurality of trenches is formed in the first substrate area that each extends through all the layers and into the silicon. A second plurality of trenches is formed in the second substrate area that each extends through the second insulation layer and into the silicon. An insulation material is formed in the first and second trenches. Logic devices are formed in the first substrate area, and memory cells are formed in the second substrate area.

    Abstract translation: 形成半导体器件的方法从硅衬底，硅上的第一绝缘层和第一绝缘层上的硅层开始。 仅从第二衬底区域去除硅层和绝缘层。 第二绝缘层形成在衬底第一区域中的硅层之上并且在第二衬底区域中的硅上方。 第一多个沟槽形成在第一衬底区域中，每个沟槽延伸穿过所有层并进入硅中。 第二多个沟槽形成在第二衬底区域中，每个沟槽延伸穿过第二绝缘层并进入硅中。 绝缘材料形成在第一和第二沟槽中。 逻辑器件形成在第一衬底区域中，并且存储器单元形成在第二衬底区域中。

    Non-volatile Memory Device And A Method Of Programming Such Device
    197.
    发明申请
    Non-volatile Memory Device And A Method Of Programming Such Device 有权
    非易失性存储器件及其编程方法

    公开(公告)号：US20150003166A1

    公开(公告)日：2015-01-01

    申请号：US14449926

    申请日：2014-08-01

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Thuan Vu

    IPC: G11C16/10 ,  G11C16/26 ,  H01L27/115

    CPC classification number: G11C16/10 ,  G11C7/00 ,  G11C7/22 ,  G11C16/26 ,  G11C16/28 ,  G11C2207/2263 ,  G11C2211/5647 ,  H01L27/11517

    Abstract: A non-volatile memory device has a charge pump for providing a programming current and an array of non-volatile memory cells. Each memory cell of the array is programmed by the programming current from the charge pump. The array of non-volatile memory cells is partitioned into a plurality of units, with each unit comprising a plurality of memory cells. An indicator memory cell is associated with each unit of non-volatile memory cells. A programming circuit programs the memory cells of each unit using the programming current, when fifty percent or less of the memory cells of each unit is to be programmed, and programs the inverse of the memory cells of each unit and the indicator memory cell associated with each unit, using the programming current, when more than fifty percent of the memory cells of each unit is to be programmed.

    Abstract translation: 非易失性存储器件具有用于提供编程电流和非易失性存储器单元阵列的电荷泵。 阵列的每个存储单元都由来自电荷泵的编程电流编程。 非易失性存储器单元的阵列被分割成多个单元，每个单元包括多个存储器单元。 指示器存储单元与每单位的非易失性存储单元相关联。 编程电路使用编程电流来对每个单元的存储器单元进行编程，当每个单元的存储单元的百分之五十或更少被编程时，编程每个单元的存储器单元的反相和与 每个单元使用编程电流时，每个单元的存储单元的百分之五十以上将被编程。

    Neural network classifier using array of three-gate non-volatile memory cells
    199.
    发明授权
    Neural network classifier using array of three-gate non-volatile memory cells 有权

    公开(公告)号：US12283314B2

    公开(公告)日：2025-04-22

    申请号：US18644840

    申请日：2024-04-24

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

    IPC: G11C11/54 ,  G06N3/045 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H10B41/30 ,  H10D30/68

    Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, fourth lines each electrically connect the drain regions in one of the memory cell columns, and a plurality of transistors each electrically connected in series with one of the fourth lines. The synapses receive a first plurality of inputs as electrical voltages on gates of the transistors, and provide a first plurality of outputs as electrical currents on the third lines.

Patent Agency Ranking