公开(公告)号：US20240339456A1

公开(公告)日：2024-10-10

申请号：US18746818

申请日：2024-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823857 ,  H01L29/42368 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78696

Abstract: A semiconductor device according to an embodiment includes a first gate-all-around (GAA) transistor and a second GAA transistor. The first GAA transistor includes a first plurality of channel members, a first interfacial layer over the first plurality of channel members, a first hafnium-containing dielectric layer over the first interfacial layer, and a metal gate electrode layer over the first hafnium-containing dielectric layer. The second GAA transistor includes a second plurality of channel members, a second interfacial layer over the second plurality of channel members, a second hafnium-containing dielectric layer over the second interfacial layer, and the metal gate electrode layer over the second hafnium-containing dielectric layer. A first thickness of the first interfacial layer is greater than a second thickness of the second interfacial layer. A third thickness of the first hafnium-containing dielectric layer is smaller than a fourth thickness of the second hafnium-containing dielectric layer.

公开(公告)号：US12113132B2

公开(公告)日：2024-10-08

申请号：US18053021

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang Chen ,  Chih-Ming Lai ,  Ching-Wei Tsai ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kuo-Cheng Chiang ,  Ru-Gun Liu ,  Wei-Hao Wu ,  Yi-Hsiung Lin ,  Chia-Hao Chang ,  Lei-Chun Chou

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/485 ,  H01L23/50 ,  H01L23/528 ,  H01L23/535 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/76871 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/41791

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US20240332391A1

公开(公告)日：2024-10-03

申请号：US18742126

申请日：2024-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guan-Lin Chen ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/78696

Abstract: A semiconductor structure includes a first stack of semiconductor layers disposed over a semiconductor substrate, where the first stack of semiconductor layers includes a first SiGe layer and a plurality of Si layers disposed over the first SiGe layer and the Si layers are substantially free of Ge, and a second stack of semiconductor layers disposed adjacent to the first stack of semiconductor layers, where the second stack of semiconductor layers includes the first SiGe layer and a plurality of second SiGe layers disposed over the first SiGe layer, and where the first SiGe layer and the second SiGe layers have different compositions. The semiconductor structure further includes a first metal gate stack interleaved with the first stack of semiconductor layers to form a first device and a second metal gate stack interleaved with the second stack of semiconductor layers to form a second device different from the first device.

公开(公告)号：US12068383B2

公开(公告)日：2024-08-20

申请号：US17813110

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Chi-Wen Liu ,  Ying-Keung Leung

IPC: H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H10B12/00

CPC classification number: H01L29/41791 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785 ,  H10B12/056 ,  H01L29/66545

Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.

公开(公告)号：US20240243178A1

公开(公告)日：2024-07-18

申请号：US18623697

申请日：2024-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/76897 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.

公开(公告)号：US12034077B2

公开(公告)日：2024-07-09

申请号：US17663267

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Chi-Wen Liu ,  Ying-Keung Leung

IPC: H01L29/78 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/165

CPC classification number: H01L29/7856 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78696 ,  H01L29/165 ,  H01L2029/7858

Abstract: A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.

公开(公告)号：US12021132B2

公开(公告)日：2024-06-25

申请号：US17858544

申请日：2022-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L29/66484 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/1033 ,  H01L29/78696

Abstract: A device includes a substrate, channel layers over the substrate, a gate dielectric layer around the channel layers, a first work function metal layer around the gate dielectric layer, a second work function metal layer over the first work function metal layer, and a passivation layer between the first work function metal layer and the second work function metal layer. The passivation layer merges in space vertically between adjacent ones of the channel layers.

公开(公告)号：US20240194676A1

公开(公告)日：2024-06-13

申请号：US18587622

申请日：2024-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.

公开(公告)号：US11996298B2

公开(公告)日：2024-05-28

申请号：US17890980

申请日：2022-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Jia-Ni Yu ,  Chun-Fu Lu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L21/00 ,  H01L21/475 ,  H01L21/4757 ,  H01L21/477 ,  H01L27/088

CPC classification number: H01L21/477 ,  H01L21/475 ,  H01L21/47573 ,  H01L27/0886

Abstract: A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.

公开(公告)号：US11948987B2

公开(公告)日：2024-04-02

申请号：US17016109

申请日：2020-09-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/76897 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.