公开(公告)号：US20050034041A1

公开(公告)日：2005-02-10

申请号：US10876372

申请日：2004-06-24

Applicant: Marco Casarsa

Inventor： Marco Casarsa

IPC: G01R31/00 ,  G01R31/30 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3187 ,  G01R31/28

CPC classification number: G01R31/31724 ,  G01R31/006 ,  G01R31/3004 ,  G01R31/318547 ,  G01R31/318577 ,  G01R31/3187

Abstract: An integrated device including a functional circuitry and a built-in self testing circuit for executing a structured test on the functional circuitry is proposed. The functional circuitry includes means for receiving input test values from the built-in self testing circuit and returning output test values to the built-in self testing circuit. In the solution of the invention, the built-in self testing circuit includes a memory for storing starting test values and expected test values, means for generating the input test values according to the starting test values, and means for determining a result of the structured test according to a comparison between the output test values and the expected test values.

Abstract translation: 提出了一种集成装置，其包括功能电路和用于在功能电路上执行结构化测试的内置自检电路。 功能电路包括用于从内置自检电路接收输入测试值并将输出测试值返回到内置自测电路的装置。 在本发明的解决方案中，内置的自检电路包括用于存储起始测试值和预期测试值的存储器，用于根据起始测试值生成输入测试值的装置，以及用于确定结构化结果的结果的装置 根据输出测试值和预期测试值之间的比较进行测试。

公开(公告)号：US20050031057A1

公开(公告)日：2005-02-10

申请号：US10888088

申请日：2004-07-09

Applicant: Ettore Messina ,  Nicolo Piazzese ,  Giuseppe Lippolis ,  Elena Salurso ,  Alberto Serratore ,  Agostino Galluzzo

Inventor： Ettore Messina ,  Nicolo Piazzese ,  Giuseppe Lippolis ,  Elena Salurso ,  Alberto Serratore ,  Agostino Galluzzo

IPC: H03G3/20 ,  H03M1/18 ,  H04L27/08

CPC classification number: H03G3/3052 ,  H03G3/3036 ,  H03M1/185

Abstract: A method for automatic gain control of an output signal generated from an input signal includes measuring power of the output signal. Measuring power of the output signal includes setting at least one power threshold, measuring a rate of crossing of the at least one power threshold by the output signal over an observation window, and deriving from the rate of crossing a measured power of the output signal. The method further includes providing a reference power, subtracting the measured power from the reference power to obtain an error signal, and mixing the input signal with the error signal. An analog-to-digital conversion is performed on a result of the mixing to obtain a gain-controlled output signal.

Abstract translation: 用于对从输入信号产生的输出信号进行自动增益控制的方法包括测量输出信号的功率。 输出信号的测量功率包括设置至少一个功率阈值，通过观测窗口测量所述至少一个功率阈值与所述输出信号的交叉速率，以及从所述输出信号的测量功率的交叉速率导出。 该方法还包括提供参考功率，从参考功率中减去测量的功率以获得误差信号，以及将输入信号与误差信号混合。 对混合的结果执行模数转换以获得增益控制的输出信号。

公开(公告)号：US20040230869A1

公开(公告)日：2004-11-18

申请号：US10805182

申请日：2004-03-19

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Roberto Ravasio

IPC: H05K010/00

CPC classification number: G06F11/1068 ,  G06F11/1048

Abstract: An embodiment of the present invention relates to an integrated memory system comprising at least a non-volatile memory and an automatic storage error corrector, and wherein the memory is connected to a controller by means of an interface bus. Advantageously, the system comprises in the memory circuit means, functionally independent, each being responsible for the correction of a predetermined storage error; at least one of said means generating a signal to ask a correction being external to the memory.

Abstract translation: 本发明的实施例涉及至少包括非易失性存储器和自动存储错误校正器的集成存储器系统，并且其中存储器通过接口总线连接到控制器。 有利地，该系统在存储器电路装置中包括功能上独立的，每个都负责校正预定的存储错误; 所述装置中的至少一个产生要求校正在存储器外部的信号。

公开(公告)号：US20040218440A1

公开(公告)日：2004-11-04

申请号：US10789443

申请日：2004-02-27

Applicant: STMicroelectronics S.r.I.

Inventor： Promod Kumar ,  Francesco Tomaiuolo ,  Pierpaolo Nicosia ,  Luca Giuseppe De Ambroggi ,  Francesco Pipitone

IPC: G11C011/34

CPC classification number: G11C29/16 ,  G11C16/04 ,  G11C2029/0401 ,  G11C2029/0405

Abstract: An effective Electric Wafer Sort (EWS) flow is implemented by expanding the functions of the micro-controller embedded in a FLASH EPROM memory device and of the integrated test structures. The architecture provides for executing test routines internally without involving any external complex or expensive test equipment to control the test program. The processes are executed by the onboard micro-controllers (that may be reading either from an embedded ROM or from a GLOBAL CACHE provided). Managing test routines by an internal process permits the device architecture to be transparent from a tester point of view, by purposely creating a standard interface with a set of defined commands and instructions to be interpreted by the on board microcontroller and internally executed.

Abstract translation: 通过扩展嵌入在FLASH EPROM存储器件和集成测试结构中的微控制器的功能来实现有效的电晶片分级（EWS）流程。 该架构提供在内部执行测试例程，而不涉及任何外部复杂或昂贵的测试设备来控制测试程序。 这些过程由板载微控制器执行（可能是从嵌入式ROM或从提供的GLOBAL CACHE读取）。 通过内部进程来管理测试例程允许设备架构从测试人员的角度来看是透明的，目的是通过一组定义的命令和指令来创建标准接口，由板载微控制器解释并在内部执行。

公开(公告)号：US20040214415A1

公开(公告)日：2004-10-28

申请号：US10758289

申请日：2004-01-15

Applicant: STMicroelectronics S.r.I. ,  OVONYX Inc.

Inventor： Fabio Pellizzer ,  Roberto Bez ,  Marina Tosi

IPC: H01L021/28

CPC classification number: H01L21/823835 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: A process wherein an insulating region is formed in a body at least around an array portion of a semiconductor body; a gate electrode of semiconductor material is formed on top of a circuitry portion of the semiconductor body; a first silicide protection mask is formed on top of the array portion; the gate electrode and the active areas of the circuitry portion are silicided and the first silicide protection mask is removed. The first silicide protection mask (is of polysilicon and is formed simultaneously with the gate electrode. A second silicide protection mask of dielectric material covering the first silicide protection mask is formed before silicidation of the gate electrode. The second silicide protection mask is formed simultaneously with spacers formed laterally to the gate electrode.

Abstract translation: 一种绝缘区域至少在半导体本体的阵列部分周围形成在主体中的工艺; 半导体材料的栅电极形成在半导体本体的电路部分的顶部; 在阵列部分的顶部形成第一硅化物保护掩模; 栅电极和电路部分的有源区被硅化，并且去除第一硅化物保护掩模。 第一硅化物保护掩模（多晶硅，并与栅电极同时形成）在栅极电极硅化之前形成覆盖第一硅化物保护掩模的第二硅化物保护掩模，第二硅化物保护掩膜与 间隔件横向形成到栅电极。

公开(公告)号：US20040202244A1

公开(公告)日：2004-10-14

申请号：US10757368

申请日：2004-01-13

Applicant: STMicroelectronics S.r.I.

Inventor： Francesco Pappalardo ,  Agatino Pennisi

IPC: H04B001/66

CPC classification number: G06F13/423 ,  Y02D10/14 ,  Y02D10/151

Abstract: N binary signals are transmitted through a bus of m leads, where m

Abstract translation: 通过在第二信号上对第一信号进行编码，以一串时钟脉冲的节奏通过m引线的总线m

公开(公告)号：US20040174441A1

公开(公告)日：2004-09-09

申请号：US10732186

申请日：2003-12-10

Applicant: STMicroelectronics S.r.I

Inventor： Alfio Castorina ,  Sebastiano Battiato ,  Mirko Guarnera ,  Filippo Vella

IPC: H04N009/73 ,  H04N005/235 ,  H04N005/217

CPC classification number: H04N5/23293 ,  H04N9/73

Abstract: A method of processing digital video signals produced by a sensor that are to be presented on a viewfinder, the method involving: a first pair of processing operations for scaling and color interpolation; and a second pair of processing operations for the formation of a color matrix and for white balancing. The operations of at least one, and preferably of both of the pairs of processing operations are executed in a single step. The operation of white balancing is moreover performed only for one frame out of K frame in the frame sequence. The preferential application is in the construction of viewfinders for videocameras and digital still cameras.

Abstract translation: 一种处理要呈现在取景器上的由传感器产生的数字视频信号的方法，所述方法涉及：用于缩放和颜色插值的第一对处理操作; 以及用于形成彩色矩阵和用​​于白平衡的第二对处理操作。 在一个步骤中执行至少一个，优选两个处理操作对的操作。 此外，在帧序列中仅对K帧中的一帧执行白平衡的操作。 优先应用是为视频摄像机和数码相机拍摄取景器。

公开(公告)号：US20040152267A1

公开(公告)日：2004-08-05

申请号：US10715887

申请日：2003-11-18

Applicant: STMicroelectronics S.r.I.

Inventor： Paola Zuliani ,  Elisabetta Palumbo ,  Marina Scaravaggi ,  Roberto Annunziata

IPC: H01L021/336

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

Abstract: A process for manufacturing a byte selection transistor for a matrix of non volatile memory cells organised in rows and columns integrated on a semiconductor substrate, each memory cell comprising a floating gate transistor and a selection transistor, the process providing the following steps: defining on a same semiconductor substrate respective active areas for the byte selection transistor, for the floating gate transistor and for the selection transistor split by portions of insulating layer; depositing a multilayer structure comprising at least a gate oxide layer, a first polysilicon layer, a dielectric layer on the whole substrate and a second polysilicon layer, characterised in that it comprises the following steps: removing through a traditional photolithographic technique the multilayer structure to form at least a couple of two bands developing substantially in a parallel way to the columns of the matrix of memory cells, the first band being effective to define the gate regions of the byte selection transistor and of the selection transistor, the second band being effective to define the gate region of the floating gate transistor, a portion of the first band further extending on the portion of insulating layer which is adjacent to the byte selection transistor, forming an opening in the portion up to expose the first polysilicon layer, forming a conductive layer in the opening to put said first polysilicon layer in electric contact with said second polysilicon layer.

Abstract translation: 一种用于制造用于集成在半导体衬底上的行和列组织的非易失性存储器单元的矩阵的字节选择晶体管的处理，每个存储单元包括浮置栅晶体管和选择晶体管，该过程提供以下步骤： 相同的半导体衬底用于字节选择晶体管的相应有效区域，用于浮置栅极晶体管和用于分离绝缘层的选择晶体管; 沉积包括至少栅极氧化物层，第一多晶硅层，整个衬底上的电介质层和第二多晶硅层的多层结构，其特征在于其包括以下步骤：通过传统的光刻技术去除形成的多层结构 至少两个条带基本上以并行方式发展到存储器单元矩阵的列，第一条带有效地限定字节选择晶体管和选择晶体管的栅极区域，第二条带有效地 限定浮栅晶体管的栅极区，第一带的一部分在绝缘层的与字节选择晶体管相邻的部分上进一步延伸，在该部分中形成开口以暴露第一多晶硅层，形成导电 以使所述第一多晶硅层与所述第二多晶硅层电接触。

公开(公告)号：US20040136242A1

公开(公告)日：2004-07-15

申请号：US10614693

申请日：2003-07-07

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Ilaria Motta ,  Marco Capovilla

IPC: G11C005/00

CPC classification number: G11C16/12 ,  G11C5/145 ,  G11C8/08 ,  G11C2207/2227

Abstract: Voltage booster device (3) such as to selectively assume an active status and a stand-by status, said device comprising: a first terminal (15) such as to assume a respective electric potential and associated to a first capacitor (16), a second terminal (10) associated to a second capacitor (11) and selectively connectable to the first terminal (15), characterised in that it also comprises circuital means (100) for discharging the first capacitor thus reducing in module the electrical potential of the first terminal (15), the circuital means being activated to functioning when said device in the stand-by status and the second terminal (10) is disconnected from said first terminal (15).

Abstract translation: 电压升压装置（3），例如选择性地呈现活动状态和待机状态，所述装置包括：第一端子（15），以便呈现相应的电位并与第一电容器（16）相关联， 与第二电容器（11）相关并且可选择地连接到第一端子（15）的第二端子（10），其特征在于，其还包括用于对第一电容器进行放电的电路装置（100），从而减少模块中的第一电容器 当所述处于待机状态的设备和所述第二终端（10）与所述第一终端（15）断开连接时，所述电路装置被激活以起作用。

公开(公告)号：US20040124494A1

公开(公告)日：2004-07-01

申请号：US10608855

申请日：2003-06-27

Applicant: STMicroelectronics S.r.I.

Inventor： Francesco Ciovacco ,  Chiara Savardi ,  Roberto Colombo

IPC: H01L029/00

CPC classification number: H01L21/76232 ,  H01L21/3065 ,  H01L21/3086

Abstract: A process for forming trenches with an oblique profile and rounded top corners, including the steps of: in a semiconductor wafer, through a first polymerizing etch, forming depressions delimited by rounded top corners; and through a second polymerizing etch, opening trenches at the depressions. The second polymerizing etch is made in variable plasma conditions, so that the trenches have oblique walls with a constant slope.

Abstract translation: 一种用于形成具有倾斜轮廓和圆形顶角的沟槽的方法，包括以下步骤：在半导体晶片中，通过第一聚合蚀刻，形成由圆角顶角限定的凹陷; 并通过第二聚合蚀刻，在凹陷处打开沟槽。 在可变等离子体条件下进行第二次聚合蚀刻，使得沟槽具有斜率为斜率的倾斜壁。