公开(公告)号：US09460971B2

公开(公告)日：2016-10-04

申请号：US14955801

申请日：2015-12-01

Applicant: STMICROELECTRONICS, INC. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas Loubet ,  Sylvain Maitrejean ,  Romain Wacquez

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324 ,  H01L21/266 ,  H01L21/306 ,  H01L21/02 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/845 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/7849

Abstract: Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained, semiconductor-on-insulator substrate may be processed to form the differently-strained regions in the original semiconductor layer. The differently-strained regions may have opposite types of strain. The strains in the different regions may be formed independently.

公开(公告)号：US20160284822A1

公开(公告)日：2016-09-29

申请号：US15178853

申请日：2016-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/02 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.

Abstract translation: 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片。 在半导体鳍片的端部附近和相邻的半导体鳍片之间的空间内形成至少一个电介质层。 在半导体翅片的端部处邻近最外半导体翅片形成一对侧壁间隔物。 去除该对侧壁间隔物之间​​的至少一个电介质层和半导体翅片的端部。 源极/漏极区域形成在该对侧壁间隔物之间​​。

公开(公告)号：US20160284599A1

公开(公告)日：2016-09-29

申请号：US15179620

申请日：2016-06-10

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

IPC: H01L21/8234 ,  H01L21/285 ,  H01L21/84

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filled with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

Abstract translation: 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地被金属材料填充以形成埋在衬底中的源极（或漏极）触点。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。

公开(公告)号：US20160276480A1

公开(公告)日：2016-09-22

申请号：US15169495

申请日：2016-05-31

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Qing LIU ,  Thomas SKOTNICKI

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7838 ,  H01L21/28114 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.

公开(公告)号：US20160255017A1

公开(公告)日：2016-09-01

申请号：US15132521

申请日：2016-04-19

Applicant: STMicroelectronics, Inc.

Inventor： Mahesh Chowdhary ,  Sankalp Dayal

IPC: H04L12/933 ,  H04W4/02

CPC classification number: H04W4/026 ,  H04W4/027 ,  H04W88/02

Abstract: Disclosed herein is a sensor chip including at least one sensing device and a control circuit. The control circuit is configured to receive configuration data as input, and acquire data from the at least one sensing device in accordance with the configuration data. The control circuit classifies a context of the at least one sensing device relative to its surroundings based on analysis of the acquired data in accordance with the configuration data.

Abstract translation: 本文公开了包括至少一个感测装置和控制电路的传感器芯片。 控制电路被配置为接收配置数据作为输入，并且根据配置数据从至少一个感测装置获取数据。 控制电路根据配置数据对所获取的数据的分析，对至少一个感测装置的上下文相对于其周围进行分类。

公开(公告)号：US20160252542A1

公开(公告)日：2016-09-01

申请号：US14749118

申请日：2015-06-24

Applicant: STMicroelectronics, Inc.

Inventor： Mahesh Chowdhary ,  Sankalp Dayal

IPC: G01P1/07 ,  G01P15/00 ,  G01C19/32 ,  G01P1/02

CPC classification number: G01C19/32 ,  G01C19/5776 ,  G01P15/18

Abstract: An electronic device includes a printed circuit board (PCB) having at least one conductive trace thereon. A system on chip (SoC) is mounted on the PCB and electrically coupled to the conductive trace. A sensor chip is mounted on the PCB in a spaced apart relation with the SoC and electrically coupled to the conductive trace such that the sensor chip and SoC are electrically coupled. The sensor chip includes an accelerometer and/or a gyroscope, and a control circuit. The control circuit is configured to receive configuration data as input, acquire data from the accelerometer and/or the gyroscope. The control circuit is also configured to process the data so as to generate a context of the electronic device relative to its surroundings, the processing being performed in using a processing technique operating in accordance with the configuration data, and output the context.

Abstract translation: 电子设备包括其上具有至少一个导电迹线的印刷电路板（PCB）。 片上系统（SoC）安装在PCB上并与导电迹线电耦合。 传感器芯片以与SoC间隔的关系安装在PCB上，并电耦合到导电迹线，使得传感器芯片和SoC电耦合。 传感器芯片包括加速度计和/或陀螺仪，以及控制电路。 控制电路被配置为接收配置数据作为输入，从加速度计和/或陀螺仪获取数据。 控制电路还被配置为处理数据以便相对于其周围环境生成电子设备的上下文，该处理是使用根据配置数据操作的处理技术来执行的，并输出上下文。

公开(公告)号：US09412928B2

公开(公告)日：2016-08-09

申请号：US13797072

申请日：2013-03-12

Applicant: STMicroelectronics, Inc.

Inventor： William Donley

IPC: H01L35/32 ,  H01L35/28 ,  B32B38/06 ,  B32B38/10

CPC classification number: H01L35/32 ,  B32B38/06 ,  B32B38/10 ,  B32B2310/024 ,  B32B2457/00 ,  H01L35/28 ,  Y10T156/10

Abstract: A thermoelectric device includes a plurality of thin-film thermoelectric elements. Each thin-film thermoelectric element is a Seebeck-Peltier device. The thin-film thermoelectric elements are electrically coupled in parallel with each other. The thermoelectric device may be fabricated using conventional semiconductor processing technologies and may be a thin-film type device.

公开(公告)号：US09412820B2

公开(公告)日：2016-08-09

申请号：US14456272

申请日：2014-08-11

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Tenko Yamashita ,  Chun-chen Yeh ,  Veeraraghavan S. Basker

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/66 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/1037 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method for making a semiconductor device may include forming a dummy gate above a semiconductor layer on an insulating layer, forming sidewall spacers above the semiconductor layer and on opposing sides of the dummy gate, forming source and drain regions on opposing sides of the sidewall spacers, and removing the dummy gate and underlying portions of the semiconductor layer between the sidewall spacers to provide a thinned channel region having a thickness less than a remainder of the semiconductor layer outside the thinned channel region. The method may further include forming a replacement gate stack over the thinned channel region and between the sidewall spacers and having a lower portion extending below a level of adjacent bottom portions of the sidewall spacers.

Abstract translation: 制造半导体器件的方法可以包括在绝缘层上形成半导体层之上的虚拟栅极，在半导体层上方形成侧壁间隔，在虚设栅极的相对侧上，在侧壁间隔物的相对侧上形成源极和漏极区域 并且在侧壁间隔物之间​​移除半导体层的虚拟栅极和下面的部分，以提供厚度小于稀薄沟道区域外的半导体层的剩余部分的薄化沟道区域。 该方法还可以包括在稀疏的沟道区域和侧壁间隔物之间​​形成替代栅极堆叠，并且具有在侧壁间隔物的相邻底部的水平面下方延伸的下部。

公开(公告)号：US09409394B2

公开(公告)日：2016-08-09

申请号：US13906466

申请日：2013-05-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Kenneth J. Stewart

IPC: B41J2/16 ,  B41J2/14

CPC classification number: B41J2/1433 ,  B41J2/16 ,  B41J2/1635 ,  B41J2202/20

Abstract: A method of making an inkjet print head may include forming, by sawing with a rotary saw blade, continuous slotted recesses in a first surface of a wafer. The continuous slotted recesses may be arranged in parallel, spaced apart relation, and each continuous slotted recess may extend continuously across the first surface. The method may further include forming discontinuous slotted recesses in a second surface of the wafer to be aligned and coupled in communication with the continuous slotted recesses to define alternating through-wafer channels and slotted recess portions. The method may further include selectively filling the residual slotted recess portions to define through-wafer ink channels.

Abstract translation: 制造喷墨打印头的方法可以包括通过用旋转锯片锯切在晶片的第一表面中形成连续的狭槽。 连续的开槽凹槽可以平行布置，间隔开的关系，并且每个连续的开槽凹槽可以连续延伸穿过第一表面。 该方法可以进一步包括在晶片的第二表面中形成不连续的开槽的凹槽，以与待连接的开槽的凹槽对准和耦合，以限定交替的晶片通道和开槽凹部。 该方法还可以包括选择性地填充剩余的开槽凹部以限定贯穿晶片墨水通道。

公开(公告)号：US09406783B2

公开(公告)日：2016-08-02

申请号：US14788737

申请日：2015-06-30

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.