公开(公告)号：US20240063178A1

公开(公告)日：2024-02-22

申请号：US17821001

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Adel A. Elsherbini ,  Xavier Francois Brun ,  Kimin Jun ,  Shawna M. Liff ,  Johanna M. Swan ,  Yi Shi ,  Tushar Talukdar ,  Feras Eid ,  Mohammad Enamul Kabir ,  Omkar G. Karhade ,  Bhaskar Jyoti Krishnatreya

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3107 ,  H01L24/16 ,  H01L24/08 ,  H01L2225/06548 ,  H01L2224/16227 ,  H01L2224/08145 ,  H01L2224/13116 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13109 ,  H01L2224/13118 ,  H01L24/13 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05613 ,  H01L2224/05609 ,  H01L2224/05605 ,  H01L24/05

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die and a through-dielectric via (TDV) surrounded by a dielectric material in a first layer, where the TDV has a greater width at a first surface and a smaller width at an opposing second surface of the first layer; a second die, surrounded by the dielectric material, in a second layer on the first layer, where the first die is coupled to the second die by interconnects having a pitch of less than 10 microns, and the dielectric material around the second die has an interface seam extending from a second surface of the second layer towards an opposing first surface of the second layer with an angle of less than 90 degrees relative to the second surface; and a substrate on and coupled to the second layer.

公开(公告)号：US20230369236A1

公开(公告)日：2023-11-16

申请号：US18358261

申请日：2023-07-25

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L25/065

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.

公开(公告)号：US11721649B2

公开(公告)日：2023-08-08

申请号：US17748877

申请日：2022-05-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Patrick Morrow ,  Henning Braunisch ,  Kimin Jun ,  Brennen Mueller ,  Shawna M. Liff ,  Johanna M. Swan ,  Paul B. Fischer

IPC: H01L23/66 ,  H01L23/64 ,  H01L23/36 ,  H01L23/49 ,  H01L23/538 ,  H01L23/34 ,  H01L49/02

CPC classification number: H01L23/645 ,  H01L23/34 ,  H01L23/66 ,  H01L28/10 ,  H01L2223/6677

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a die having a front side and a back side, the die comprising a first material and conductive contacts at the front side; and a thermal layer attached to the back side of the die, the thermal layer comprising a second material and a conductive pathway, wherein the conductive pathway extends from a front side of the thermal layer to a back side of the thermal layer.

公开(公告)号：US20230197677A1

公开(公告)日：2023-06-22

申请号：US17557622

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Stephen R. Van Doren ,  Ritu Gupta ,  Gerald S. Pasdast ,  Robert J. Munoz ,  Shawna M. Liff

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L2225/06548

Abstract: A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies arranged in an array of rows and columns in a first layer; and a second plurality of IC dies in a second layer not coplanar with the first layer. A first IC die in the first plurality is differently sized than surrounding IC dies in the first plurality, and a second IC die in the second plurality coupled to the first IC die comprises at least one of: a repeater circuitry and a fanout structure in an electrical pathway coupling the first IC die with an adjacent IC die in the first plurality.

公开(公告)号：US20220406701A1

公开(公告)日：2022-12-22

申请号：US17822200

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/498 ,  H01L23/522 ,  H01L23/64 ,  H01L49/02 ,  G05F1/46 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.

公开(公告)号：US20220399305A1

公开(公告)日：2022-12-15

申请号：US17342826

申请日：2021-06-09

Applicant: Intel Corporation

Inventor： Beomseok Choi ,  Adel A. Elsherbini ,  Han Wui Then ,  Johanna M. Swan ,  Shawna M. Liff

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/552 ,  H01L23/66 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, embedded in a first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a first magnetic conductive material; and a second microelectronic component, embedded in a second dielectric layer on the first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a second magnetic conductive material, wherein the second microelectronic component is coupled to the surface of the first microelectronic component by a hybrid bonding region, and wherein the second magnetic conductive material is coupled to the first magnetic conductive material.

公开(公告)号：US11469209B2

公开(公告)日：2022-10-11

申请号：US17129095

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/13 ,  H01L23/498 ,  H01L23/544

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

公开(公告)号：US20220278057A1

公开(公告)日：2022-09-01

申请号：US17748877

申请日：2022-05-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Patrick Morrow ,  Henning Braunisch ,  Kimin Jun ,  Brennen Karl Mueller ,  Shawna M. Liff ,  Johanna M. Swan ,  Paul B. Fischer

IPC: H01L23/64 ,  H01L23/34 ,  H01L23/66 ,  H01L49/02

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may a die having a front side and a back side, the die comprising a first material and conductive contacts at the front side; and a thermal layer attached to the back side of the die, the thermal layer comprising a second material and a conductive pathway, wherein the conductive pathway extends from a front side of the thermal layer to a back side of the thermal layer.

公开(公告)号：US20220223561A1

公开(公告)日：2022-07-14

申请号：US17708444

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Arun Chandrasekhar

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

公开(公告)号：US20220199546A1

公开(公告)日：2022-06-23

申请号：US17127382

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Gerald S. Pasdast ,  Kimin Jun ,  Zhiguo Qian ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Mohammad Enamul Kabir ,  Feras Eid ,  Kevin P. O'Brien ,  Han Wui Then

IPC: H01L23/552 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/66

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, having a first surface and an opposing second surface including a first direct bonding region at the second surface with first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component, having a first surface and an opposing second surface, including a second direct bonding region at the first surface with second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the second microelectronic component is coupled to the first microelectronic component by the first and second direct bonding regions; and a shield structure in the first direct bonding dielectric material at least partially surrounding the one or more of the first metal contacts.