公开(公告)号：US20240111628A1

公开(公告)日：2024-04-04

申请号：US17937924

申请日：2022-10-04

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  Fatma Arzum Simsek-Ege

IPC: G06F11/10

CPC classification number: G06F11/1092

Abstract: Global column repair with local column decoder circuitry and related apparatuses, methods, and computing systems are disclosed. An apparatus includes global column repair circuitry including column address drivers corresponding to respective ones of column planes of a memory array. The column address drivers are configured to, if enabled, drive a received column address signal to local column decoder circuitry local to respective ones of the column planes. The global column repair circuitry also includes match circuitry and data storage elements configured to store defective column addresses corresponding to defective column planes. The match circuitry is configured to compare a received column address indicated by the received column address signal to the defective column addresses and disable a column address driver corresponding to a defective column plane responsive to a determination that the received column address matches a defective column address associated with the defective column plane.

公开(公告)号：US11930634B2

公开(公告)日：2024-03-12

申请号：US17364379

申请日：2021-06-30

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege

IPC: H10B12/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H10B12/485 ,  H01L25/0657 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488 ,  H10B12/50 ,  H10B80/00

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising memory cells, digit lines, word lines, and at least one isolation material covering and surrounding the memory cells, the digit lines, and the word lines. An additional microelectronic device structure comprising control logic devices and at least one additional isolation material covering and surrounding the control logic devices is formed. The additional microelectronic device structure is attached to the microelectronic device structure. Contact structures are formed to extend through the at least one isolation material and the at least one additional isolation material. Some of the contact structures are coupled to some of the digit lines and some of the control logic devices. Some other of the contact structures are coupled to some of the word lines and some other of the control logic devices. Microelectronic devices, electronic systems, and additional methods are also described.

公开(公告)号：US20240081049A1

公开(公告)日：2024-03-07

申请号：US17930388

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  G11C11/4085

Abstract: A microelectronic device is disclosed including a control logic structure that includes sense amplifiers clustered around sense amplifier exit regions; an upper memory array structure underlying the control logic structure and that includes memory cells coupled to some of the sense amplifiers of the control logic structure by way of routing extending through the sense amplifier exit regions; and a lower memory array structure underlying the upper memory array structure and that includes additional memory cells coupled to some other of the sense amplifiers of the control logic structure by way of additional routing extending through the sense amplifier exit regions.

公开(公告)号：US20240071465A1

公开(公告)日：2024-02-29

申请号：US17821645

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui ,  Richard E. Fackenthal

IPC: G11C11/408 ,  G11C5/02 ,  G11C11/4091

CPC classification number: G11C11/4085 ,  G11C5/025 ,  G11C11/4091

Abstract: Methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. A memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. For example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include a gate material operable to modulate a conductivity between the first portions and the second portions. Each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material may couple the word lines with the respective second portion of the semiconductor material. Such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.

公开(公告)号：US20240071423A1

公开(公告)日：2024-02-29

申请号：US17893681

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui ,  Richard E. Facekenthal

IPC: G11C5/02 ,  G11C5/06 ,  G11C8/14 ,  H01L27/108

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  H01L27/10891

Abstract: Methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. A memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. For example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include one or more gate material portions operable to modulate a conductivity between respective first and second portions. Each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material portions may couple the word lines with the respective second portion of the semiconductor material. Such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.

公开(公告)号：US11916032B2

公开(公告)日：2024-02-27

申请号：US17562453

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Yuan He

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  G11C11/408 ,  G11C11/4091 ,  H10B12/00

CPC classification number: H01L24/08 ,  G11C11/4085 ,  G11C11/4091 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B12/30 ,  H10B12/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A microelectronic device comprises a first microelectronic device structure comprising a stack structure comprising conductive structures vertically alternating with insulative structures, a staircase structure within the stack structure, and vertical stacks of memory cells. Each vertical stack of memory cells individually comprises a vertical stack of capacitor structures, transistor structures each individually neighboring a capacitor structure of the capacitor structures, and a conductive pillar structure vertically extending through the transistor structures. The microelectronic device further comprises a second microelectronic device structure attached to the first microelectronic device structure, the second microelectronic device structure comprising a sub word line driver region comprising complementary metal-oxide-semiconductor (CMOS) circuits vertically overlying and within a horizontal area of the staircase structure, and conductive contact structures vertically extending between steps of the staircase structure and the sub word line driver region. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20240063205A1

公开(公告)日：2024-02-22

申请号：US18491702

申请日：2023-10-20

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kunal R. Parekh

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H10B12/00

CPC classification number: H01L25/18 ,  H01L25/50 ,  H01L24/83 ,  H10B12/33 ,  H10B12/036 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488 ,  H01L2224/83895 ,  H01L2224/83896

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, contact structures coupled to the digit lines, word lines coupled to the memory cells, additional contact structures coupled to the word lines, and isolation material surrounding the contact structures and the additional contact structures and overlying the memory cells. An additional microelectronic device structure assembly is formed and comprises control logic devices, further contact structures coupled to the control logic devices, and additional isolation material surrounding the further contact structures and overlying the control logic devices. The additional microelectronic device structure assembly is attached to the microelectronic device structure assembly by bonding the additional isolation material to the isolation material and by bonding the further contact structures to the contact structures and the additional contact structures. Microelectronic devices and electronic systems are also described.

公开(公告)号：US11908932B2

公开(公告)日：2024-02-20

申请号：US16936983

申请日：2020-07-23

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kevin J. Torek ,  Kamal M. Karda ,  Yunfei Gao ,  Kamal K. Muthukrishnan

IPC: H01L29/78 ,  H01L29/10 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/764 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L21/764 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/66666

Abstract: An apparatus includes at least one vertical transistor having a channel region. The channel region includes an upper region having a first width and a lower region below the upper region and having a second width smaller than the first width. The upper region defines at least one overhang portion extending laterally beyond the lower region. The at least one vertical transistor further includes gate electrodes at least partially vertically beneath the at least one overhang portion of the upper region of the channel region. Additional apparatuses and related systems and methods are also disclosed.

公开(公告)号：US20240040775A1

公开(公告)日：2024-02-01

申请号：US18478031

申请日：2023-09-29

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kunal R. Parekh ,  Terrence B. McDaniel ,  Beau D. Barry

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/50 ,  H10B12/315 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/488

Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, a first isolation material over the first semiconductor structure, and first conductive routing structures over the first semiconductor structure and surrounded by the first isolation material. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material is bonded to the first isolation material to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Control logic devices including transistors comprising portions of the first semiconductor structure are formed after forming the memory cells. Microelectronic devices, electronic systems, and additional methods are also described.

公开(公告)号：US11862628B2

公开(公告)日：2024-01-02

申请号：US17326286

申请日：2021-05-20

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege

IPC: H01L27/06 ,  G11C5/06 ,  H01L23/538 ,  H01L25/065 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0688 ,  G11C5/06 ,  H01L21/8238 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0657 ,  H01L27/092

Abstract: Methods, systems, and devices for transistor configurations for multi-deck memory devices are described. A memory device may include a first set of transistors formed in part by doping portions of a first semiconductor substrate of the memory device. The memory device may include a set of memory cells arranged in a stack of decks of memory cells above the first semiconductor substrate and a second semiconductor substrate bonded above the stack of decks. The memory device may include a second set of transistors formed in part by doping portions of the second semiconductor substrate. The stack of decks may include a lower set of one or more decks that is coupled with the first set of transistors and an upper set of one or more decks that is coupled with the second set of transistors.