公开(公告)号：US20150162092A1

公开(公告)日：2015-06-11

申请号：US14625505

申请日：2015-02-18

Applicant: Rambus Inc.

Inventor： Brent Haukness ,  Ian Shaeffer

IPC: G11C16/32 ,  G06F12/02 ,  G11C16/10

CPC classification number: G11C16/32 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C16/04 ,  G11C16/107 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/4402

Abstract: This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or pages. By performing a test transaction to program each bit of each such unit, the maximum expected programming time of each unit may be determined in advance and used for scheduling purposes. For example, in a straightforward implementation, a relatively accurate, empirically measured time limit may be identified and used to efficiently manage and schedule flash memory transactions without awaiting ultimate resolution of attempts to write to a non-responsive page. This disclosure also provides other uses of empirically-measured maximum flash memory transaction times, including via multiple memory modes and prioritized memory; for example, if a high performance mode is desired, low variation in flash memory transaction times may be tolerated, and units not satisfying these principles may be marked relatively quickly.

Abstract translation: 本公开提供了一种准确地确定与诸如设备，块或页面之类的闪速存储器细分有关的预期交易时间的方法。 通过执行测试事务来对每个这样的单元的每个位进行编程，可以预先确定每个单元的最大预期编程时间并用于调度目的。 例如，在简单的实现中，可以识别相对精确的经验测量的时间限制并用于有效地管理和调度闪速存储器事务，而不等待最终解决写入非响应页面的尝试。 本公开还提供经验测量的最大闪存交易时间的其他用途，包括经由多个存储器模式和优先存储器; 例如，如果需要高性能模式，则可以容忍闪速存储器交易时间的低变化，并且可以相对快速地标记不满足这些原理的单元。

公开(公告)号：US20150023118A1

公开(公告)日：2015-01-22

申请号：US14509572

申请日：2014-10-08

Applicant: RAMBUS INC.

Inventor： Ian Shaeffer ,  Frederick Ware ,  Craig E. Hampel

IPC: G06F3/06 ,  G11C7/22

CPC classification number: G06F3/0634 ,  G06F3/0665 ,  G06F3/0689 ,  G06F13/1694 ,  G06F2212/262 ,  G11C7/22

Abstract: In a reconfigurable data strobe-based memory system, data strobes may be re-tasked in different modes of operation. For example, in one mode of operation a differential data strobe may be used as a timing reference for a given set of data signals. In a second mode of operation, one of the components of the differential data strobe may be used as a timing reference for a first portion of the set of data signals and the other component used as a timing reference for a second portion of the set of data signals. Different data mask-related schemes also may be invoked for different modes of operation. For example, in a first mode of operation a memory controller may generate a data mask signal to prevent a portion of a set of data from being written to a memory array. Then, in a second mode of operation the memory controller may invoke a coded value replacement scheme or a data strobe transition inhibition scheme to prevent a portion of a set of data from being written to a memory array.

Abstract translation: 在可重新配置的基于数据选通的存储器系统中，数据选通可以在不同的操作模式下重新安排。 例如，在一种操作模式中，差分数据选通可以用作给定的一组数据信号的定时参考。 在第二操作模式中，可以将差分数据选通的一个组件用作数据信号组的第一部分的定时参考，另一组件用作该组数据信号的第二部分的定时参考 数据信号。 也可以针对不同的操作模式调用不同的数据掩码相关方案。 例如，在第一操作模式中，存储器控制器可以生成数据掩码信号以防止一组数据被写入存储器阵列。 然后，在第二操作模式中，存储器控制器可以调用编码值替换方案或数据选通转换禁止方案，以防止一组数据被写入存储器阵列。

公开(公告)号：US20140347950A1

公开(公告)日：2014-11-27

申请号：US14194923

申请日：2014-03-03

Applicant: Rambus Inc.

Inventor： Ian Shaeffer

IPC: G11C8/16 ,  G11C8/06

CPC classification number: G11C8/16 ,  G06F12/00 ,  G06F13/4018 ,  G06F13/4243 ,  G11C8/06

Abstract: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

Abstract translation: 描述的是使用固定宽度内存模块支持动态点对点可扩展性的内存模块。 存储器模块包括数据宽度转换器，其允许模块改变其外部存储器接口的有效宽度，而不改变在转换器和相关联的固定宽度管芯之间延伸的内部存储器接口的宽度。 数据宽度转换器使用数据掩码信号来选择性地阻止对物理地址子集的存储器访问。 该数据屏蔽将物理地址位置划分为物理地址位置的两个或更多个时间子集，从而有效地增加给定模块中唯一可寻址位置的数量。 以写入顺序读取时间地址可能会引入不期望的读取延迟。 一些实施例重新排序读取数据以减少该等待时间。

公开(公告)号：US20130194854A1

公开(公告)日：2013-08-01

申请号：US13753360

申请日：2013-01-29

Applicant: RAMBUS INC.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C5/06

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/18 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.