公开(公告)号：US10193090B2

公开(公告)日：2019-01-29

申请号：US15627722

申请日：2017-06-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Lu ,  Jean-Pierre Colinge ,  Ken-Ichi Goto ,  Zhiqiang Wu ,  Yu-Ming Lin

IPC: H01L51/05 ,  H01L51/00 ,  H01L51/10

Abstract: In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.

公开(公告)号：US10056473B1

公开(公告)日：2018-08-21

申请号：US15481748

申请日：2017-04-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hao Wang ,  Wai-Yi Lien ,  Gwan-Sin Chang ,  Yu-Ming Lin ,  Ching Hsueh ,  Jia-Chuan You ,  Chia-Hao Chang

IPC: H01L21/335 ,  H01L21/8232 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/7855

Abstract: A method for manufacturing a semiconductor device, including forming a dummy gate structure on a substrate, in which the substrate has a source/drain portion and a channel portion adjacent to the source/drain region, and the dummy gate structure is formed on the channel portion of the substrate; recessing at least a part of the source/drain portion to form a recess in the source/drain portion of the substrate; forming a stress material in the recess; replacing the dummy gate structure with a gate stack; removing the stress material in the recess after the replacing the dummy gate structure with the gate stack; and forming an epitaxy structure in the recess.

公开(公告)号：US12302636B2

公开(公告)日：2025-05-13

申请号：US17869086

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Han-Jong Chia

IPC: H01L27/12 ,  G11C11/22 ,  H01L21/84 ,  H10B51/20 ,  H10B51/30 ,  H10D30/01 ,  H10D30/69 ,  H10D64/01 ,  H10D64/68 ,  H10D86/00 ,  H10D86/01 ,  H10D87/00

Abstract: A method for forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, wherein each of the first and the second layer stacks comprises a dielectric layer, a channel layer, and a source/drain layer formed successively over the substrate; forming openings that extend through the first layer stack and the second layer stack, where the openings include first openings within boundaries of the first and the second layer stacks, and a second opening extending from a sidewall of the second layer stack toward the first openings; forming inner spacers by replacing portions of the source/drain layer exposed by the openings with a dielectric material; lining sidewalls of the openings with a ferroelectric material; and forming first gate electrodes in the first openings and a dummy gate electrode in the second opening by filling the openings with an electrically conductive material.

公开(公告)号：US12224212B2

公开(公告)日：2025-02-11

申请号：US18323907

申请日：2023-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/764 ,  H01L23/528 ,  H01L27/088 ,  H01L29/417

Abstract: A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain epitaxial features; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside; and a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.

公开(公告)号：US20240389334A1

公开(公告)日：2024-11-21

申请号：US18785757

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H10B51/20 ,  G11C11/22 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H10B43/20 ,  H10B43/27 ,  H10B51/10 ,  H10B51/30

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

公开(公告)号：US20240387696A1

公开(公告)日：2024-11-21

申请号：US18785670

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/768

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

公开(公告)号：US12094942B2

公开(公告)日：2024-09-17

申请号：US17815089

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/285 ,  H01L21/321 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/535 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/28568 ,  H01L21/3212 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/535 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a metal gate structure (MG) formed over a substrate, a first gate spacer formed on a first sidewall of the MG, a second gate spacer formed on a second sidewall of the MG opposite to the first sidewall, where the second gate spacer is shorter than the first gate spacer, a source/drain (S/D) contact (MD) adjacent to the MG, where a sidewall of the MD is defined by the second gate spacer, and a contact feature configured to electrically connect the MG to the MD.

公开(公告)号：US12009254B2

公开(公告)日：2024-06-11

申请号：US17745127

申请日：2022-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin

IPC: H01L21/321 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7684 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53209

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

公开(公告)号：US20240164109A1

公开(公告)日：2024-05-16

申请号：US18406745

申请日：2024-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H10B51/20 ,  H01L23/535 ,  H01L29/417 ,  H10B51/00 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L23/535 ,  H01L29/41741 ,  H01L29/41775 ,  H10B51/00 ,  H10B51/10 ,  H10B51/30

Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.

公开(公告)号：US11955515B2

公开(公告)日：2024-04-09

申请号：US17815761

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chuan Chiu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Chun-Yuan Chen ,  Li-Zhen Yu ,  Yu-Ming Lin

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L21/823418 ,  H01L29/42392

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.