公开(公告)号：US10529826B1

公开(公告)日：2020-01-07

申请号：US16101876

申请日：2018-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Chanro Park ,  Kangguo Cheng

IPC: H01L29/66 ,  H01L21/764 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423

Abstract: A method includes forming an active layer, forming a gate structure above a channel region of the active layer, forming a sidewall spacer adjacent the gate structure, forming a first dielectric layer adjacent the sidewall spacer, recessing the gate structure to define a gate cavity, forming an inner spacer in the gate cavity, forming a cap layer in the gate cavity, recessing the first dielectric layer and the sidewall spacer to expose sidewall surfaces of the cap layer, removing the inner spacer to define a first spacer cavity, forming an upper spacer in the spacer cavity and contacting sidewall surfaces of the cap layer, forming a second dielectric layer above the upper spacer and the cap layer, and forming a first contact structure at least partially embedded in the second dielectric layer and contacting a surface of the upper spacer.

公开(公告)号：US10388732B1

公开(公告)日：2019-08-20

申请号：US15992942

申请日：2018-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Nicolas Loubet ,  Kangguo Cheng ,  Juntao Li

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/08 ,  H01L29/423 ,  H01L29/24 ,  H01L29/16 ,  H01L21/02 ,  H01L21/04 ,  H01L29/66 ,  H01L21/423 ,  H01L21/441 ,  H01L29/10

Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A plurality of channel layers are arranged in a layer stack, and a source/drain region is connected with the plurality of channel layers. A gate structure includes a plurality of sections that respectively surround the plurality of channel layers. The plurality of channel layers contain a two-dimensional semiconducting material.

公开(公告)号：US10373873B1

公开(公告)日：2019-08-06

申请号：US15933708

申请日：2018-03-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Ruilong Xie ,  Kangguo Cheng ,  Laertis Economikos

IPC: H01L21/8234 ,  H01L29/66

Abstract: Gate isolation methods and structures for a FinFET device leverage the definition and formation of a gate cut opening within a sacrificial gate layer prior to patterning the sacrificial gate layer to form a sacrificial gate. The gate cut opening formed in the sacrificial gate layer is filled with a sacrificial isolation layer. After forming source/drain junctions over source/drain regions of a fin, the sacrificial isolation layer is replaced with an isolation layer, and the sacrificial gate is replaced with a functional gate.

公开(公告)号：US10366930B1

公开(公告)日：2019-07-30

申请号：US16005064

申请日：2018-06-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Kangguo Cheng ,  Guillaume Bouche

IPC: H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66

Abstract: A method includes forming a plurality of fins above a substrate. A first placeholder gate electrode is formed above the plurality of fins. The first placeholder gate electrode includes a placeholder material. A first sacrificial gate cut structure of a sacrificial material different than the placeholder material embedded in the first placeholder gate electrode is formed. A portion of the first placeholder gate electrode positioned above the first sacrificial gate cut structure is removed, exposing the first sacrificial gate cut structure. The first sacrificial gate cut structure is removed to define a gate cut cavity extending vertically through the first placeholder gate electrode. A dielectric material is formed in the gate cut cavity to define a gate cut structure. The first placeholder gate electrode is removed to define a first gate cavity segmented by the gate cut structure. A first replacement gate structure is formed in the first gate cavity.

公开(公告)号：US10319731B2

公开(公告)日：2019-06-11

申请号：US15673548

申请日：2017-08-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Tenko Yamashita ,  Kangguo Cheng

IPC: H01L27/11556 ,  H01L27/11526 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/423 ,  H01L27/088 ,  H01L29/788

Abstract: The disclosure is directed to an integrated circuit structure and method of forming the same. The integrated circuit structure may include: a first device region including: a floating gate structure substantially surrounding a first fin that is over a substrate; a first bottom source/drain within the substrate, and beneath the first fin and the floating gate structure; a first top source/drain over the first fin and the floating gate structure; a first spacer substantially surrounding the first top source/drain and disposed over the floating gate structure; and a gate structure substantially surrounding and insulated from the floating gate structure, the gate structure being disposed over the substrate and having a height greater than a height of the floating gate.

公开(公告)号：US10297452B2

公开(公告)日：2019-05-21

申请号：US15712301

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hui Zang ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: One illustrative method disclosed includes selectively forming sacrificial conductive source/drain cap structures on and in contact with first and second source/drain contact structures positioned on opposite sides of a gate of a transistor and removing and replacing the spaced-apart sacrificial conductive source/drain cap structures with first and second separate, laterally spaced-apart insulating source/drain cap structures that are positioned on the first and second source/drain contact structures. The method also includes forming a gate contact opening that extends through a space between the insulating source/drain cap structures and through the gate cap so as to expose a portion of the gate structure and forming a conductive gate contact structure (CB) that is conductively coupled to the gate structure.

公开(公告)号：US20190148557A1

公开(公告)日：2019-05-16

申请号：US16242834

申请日：2019-01-08

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L21/321 ,  H01L21/02

Abstract: A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.

公开(公告)号：US10290574B2

公开(公告)日：2019-05-14

申请号：US15408883

申请日：2017-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Geng Wang ,  Kangguo Cheng ,  Chengwen Pei ,  Juntao Li

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/822 ,  H01L23/528 ,  H01L21/768

Abstract: Various embodiments include three-dimensional (3D) integrated circuit (IC) structures and methods of forming such structures. In some cases, a 3D IC structure includes: a substrate; a first set of transistors overlying the substrate; a first inter-level dielectric (ILD) overlying the first set of transistors and the substrate; a dielectric overlying the first ILD; a semiconductor layer overlying the dielectric; a second set of transistors overlying the semiconductor layer; a capacitor embedded within the dielectric; and a first contact extending through the semiconductor layer and the dielectric to contact one layer of the capacitor, and a second contact extending through the semiconductor layer and the dielectric to contact a second, distinct layer of the capacitor.

公开(公告)号：US10158003B2

公开(公告)日：2018-12-18

申请号：US14824349

申请日：2015-08-12

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Zuoguang Liu ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/324 ,  H01L29/45 ,  H01L27/088 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267

Abstract: A method of making a semiconductor device includes forming a fin in a substrate; depositing a first spacer material to form a first spacer around the fin; depositing a second spacer material to form a second spacer over the first spacer; recessing the first spacer and the second spacer; removing the first spacer; and performing an epitaxial growth process to form epitaxial growth on an end of the fin, along a sidewall of the fin, and adjacent to the fin.

公开(公告)号：US20180277648A1

公开(公告)日：2018-09-27

申请号：US15986031

申请日：2018-05-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/20 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/3065 ,  H01L29/10

Abstract: Methods for forming a semiconductor device include forming a first spacer on a plurality of fins. A second spacer is formed on the first spacer, the second spacer being formed from a different material from the first spacer. Gaps between the fins are filled with a support material. The first spacer and second spacer are polished to expose a top surface of the plurality of fins. All of the support material is etched away after polishing the first spacer and second spacer. The plurality of fins is etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched plurality of fins to fill the fin cavity.