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公开(公告)号：US20180006217A1
公开(公告)日：2018-01-04
申请号：US15689256
申请日：2017-08-29
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Innocenzo Tortorelli , Andrea Ghetti
CPC classification number: H01L45/06 , H01L27/2427 , H01L27/2463 , H01L27/249 , H01L45/1233 , H01L45/144 , H01L45/1675
Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.
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公开(公告)号：US20170352414A1
公开(公告)日：2017-12-07
申请号：US15686308
申请日：2017-08-25
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Roberto Bez , Ferdinando Bedeschi , Roberto Gastaldi
CPC classification number: G11C13/0004 , G11C11/56 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2213/79 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144
Abstract: A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.
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213.发明授权公开(公告)号：US09755145B2
公开(公告)日：2017-09-05
申请号：US15279158
申请日：2016-09-28
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Giorgio Servalli , Carmela Cupeta , Fabio Pellizzer
CPC classification number: H01L45/1293 , H01L27/2463 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/126 , H01L45/1286 , H01L45/141 , H01L45/144 , H01L45/1608 , H01L45/1666 , H01L45/1675
Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.
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公开(公告)号：US20170186487A1
公开(公告)日：2017-06-29
申请号：US15399530
申请日：2017-01-05
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Fabio Pellizzer , Ferdinando Bedeschi
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0004 , G11C13/0028 , G11C13/0033 , G11C13/0069 , G11C13/0097 , G11C2013/0047 , G11C2013/0057 , G11C2213/72
Abstract: A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.
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公开(公告)号：US09672908B2
公开(公告)日：2017-06-06
申请号：US14977411
申请日：2015-12-21
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Fabio Pellizzer
CPC classification number: G11C13/004 , G11C11/5678 , G11C13/0004 , G11C2013/0045 , G11C2013/0057
Abstract: The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. The method additionally comprises determining whether a threshold voltage (Vth) of the memory cell has a value within a predetermined read voltage window. A test pulse is applied to the memory cell if it is determined that the threshold voltage has a value within the predetermined read voltage window. The state of the memory cell may be determined based on a response of the memory cell to the test pulse, wherein the state corresponds to the one of the pluralities of states of the memory cell prior to receiving the test pulse.
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Patent Agency Ranking
公开(公告)号：US09634063B2
公开(公告)日：2017-04-25
申请号：US14799471
申请日：2015-07-14
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Fabio Pellizzer , Antonino Rigano , Marcello Mariani , Augusto Benvenuti
IPC: H01L21/335 , H01L27/24 , H01L45/00 , H01L29/423 , H01L21/762 , G11C13/00 , H01L21/308
CPC classification number: H01L27/2445 , G11C13/0004 , H01L21/3086 , H01L21/762 , H01L27/2463 , H01L29/42304 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/16 , H01L45/1675
Abstract: Embodiments disclosed herein may relate to forming a contact region for an interconnect between a selector transistor and a word-line electrode in a memory device.
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公开(公告)号：US09620713B2
公开(公告)日：2017-04-11
申请号：US14820046
申请日：2015-08-06
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer
CPC classification number: H01L45/16 , H01L27/2427 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/144 , H01L45/1675
Abstract: Memory cells, arrays of memory cells, and methods of forming the same with sealing material on sidewalls thereof are disclosed herein. One example of forming a memory cell includes forming a stack of materials, forming a trench to a first depth in the stack of materials such that a portion of at least one of the active storage element material and the active select device material is exposed on sidewalls of the trench. A sealing material is formed on the exposed portion of the at least one of the active storage element material and the active select device material and the trench is deepened such that a portion of the other of the at least one of the active storage element material and the active select device material is exposed on the sidewalls of the trench.
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公开(公告)号：US20170062715A1
公开(公告)日：2017-03-02
申请号：US15347271
申请日：2016-11-09
Applicant: Micron Technology, Inc.
Inventor： Antonino Rigano , Fabio Pellizzer
CPC classification number: H01L45/1691 , G11C13/0004 , G11C13/0023 , G11C13/0038 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/065 , H01L45/12 , H01L45/124 , H01L45/128 , H01L45/143 , H01L45/144 , H01L45/16
Abstract: Clamp elements, memories, apparatuses, and methods for forming the same are disclosed herein. An example memory may include an array of memory cells and a plurality of clamp elements. A clamp element of the plurality of clamp elements may include a cell structure formed non-orthogonally relative to at least one of a bit line or a word line of the array of memory cells and may be configured to control a voltage of a respective bit line.
Abstract translation: 本文公开了夹紧元件，存储器，装置及其形成方法。 示例性存储器可以包括存储器单元阵列和多个钳位元件。 多个钳位元件的钳位元件可以包括相对于存储器单元阵列的位线或字线中的至少一个非正交形成的单元结构，并且可以被配置为控制相应位线的电压 。
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公开(公告)号：US09570681B2
公开(公告)日：2017-02-14
申请号：US14491713
申请日：2014-09-19
Applicant: Micron Technology, Inc.
Inventor： Cristina Casellato , Carmela Cupeta , Michele Magistretti , Fabio Pellizzer , Roberto Somaschini
IPC: H01L45/00 , H01L23/528 , H01L27/24 , H01L23/532 , H01L27/10
CPC classification number: H01L45/16 , H01L23/5283 , H01L23/53295 , H01L27/101 , H01L27/24 , H01L27/2436 , H01L27/2463 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L2924/0002 , H01L2924/00
Abstract: A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. The metallization may form row lines in the array.
Abstract translation: 电阻随机存取存储器可以包括存储器阵列和围绕存储器阵列的周边。 外围的解码器可以通过使用相同的金属沉积在同一时间在周边和阵列中形成金属化而耦合到阵列中的地址线。 金属化可以在阵列中形成行线。
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公开(公告)号：US09443562B2
公开(公告)日：2016-09-13
申请号：US14982362
申请日：2015-12-29
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Everardo Torres Flores , Hernan A. Castro
IPC: G11C11/00 , G11C5/06 , H01L27/02 , H01L23/528 , G11C13/00
CPC classification number: H01L23/528 , G11C5/025 , G11C5/063 , G11C13/0004 , G11C13/0028 , G11C2213/77 , H01L21/768 , H01L27/0207 , H01L27/2427 , H01L27/2463 , H01L2924/0002 , H01L2924/00
Abstract: Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line electrodes may be configured to form a socket area to provide connection points to drivers and/or other circuitry that may be located within a footprint of an array of memory cells.
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