公开(公告)号：US09459962B2

公开(公告)日：2016-10-04

申请号：US14330866

申请日：2014-07-14

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  G06F3/06 ,  H04L1/00 ,  H03M13/29 ,  G11C29/52

CPC classification number: G06F11/108 ,  G06F3/0679 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1012 ,  G06F11/1068 ,  G06F11/1076 ,  G06F2211/109 ,  G11C29/52 ,  H03M13/29 ,  H04L1/0061

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. A multiplexer is controlled to couple a DRAM (Dynamic Random Access Memory) to a buffer. A DMA (Direct Memory Access) controller is directed to store a message of the DRAM to the buffer through the multiplexer and to output the message of the DRAM to a RAID-encoding (Redundant Array of Independent Disk-encoding) unit in multiple batches. After a first condition is satisfied, the processing unit controls the multiplexer to couple the RAID-encoding unit to the buffer and directs the RAID-encoding unit to output a vertical ECC (Error Correction Code) to the buffer through the multiplexer in at least one batch.

Abstract translation: 用于访问由处理单元执行的闪速存储器的存储单元的方法的实施例至少包括以下步骤。 控制多路复用器将DRAM（动态随机存取存储器）耦合到缓冲器。 DMA（直接存储器访问）控制器被指示通过多路复用器将DRAM的消息存储到缓冲器，并将DRAM的消息以多个批次的形式输出到RAID编码（独立磁盘编码冗余阵列）单元。 在满足第一条件之后，处理单元控制多路复用器将RAID编码单元耦合到缓冲器，并引导RAID编码单元通过多路复用器至少一个输出垂直ECC（纠错码）到缓冲器 批量。

公开(公告)号：US20150370630A1

公开(公告)日：2015-12-24

申请号：US14666320

申请日：2015-03-24

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  G11C11/406 ,  G11C29/52 ,  G06F12/02

CPC classification number: G06F11/1044 ,  G06F3/0679 ,  G06F11/1048 ,  G06F11/1072 ,  G06F12/02 ,  G06F12/0246 ,  G06F2003/0691 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A flash memory controlling apparatus includes a data read/write interface and a controller. The data read/write interface is arranged to couple a first flash memory and a second flash memory, wherein the first flash memory includes a first storage plane and a first buffer, and the second flash memory includes a second storage plane and a second buffer. When the read/write interface couples the first flash memory and the second flash memory, the controller is arranged to temporary store a plurality of valid data stored in the first storage plane into the second buffer. After an erase cycle is performed on the first storage plane, the controller further programs the plurality of valid data temporarily stored in the second buffer into the first storage plane.

Abstract translation: 闪存控制装置包括数据读/写接口和控制器。 数据读/写接口被布置成耦合第一闪速存储器和第二闪速存储器，其中第一闪速存储器包括第一存储平面和第一缓冲器，并且第二闪速存储器包括第二存储平面和第二缓冲器。 当读/写接口耦合第一闪速存储器和第二闪速存储器时，控制器被布置为将存储在第一存储平面中的多个有效数据临时存储到第二缓冲器中。 在第一存储平面执行擦除周期之后，控制器还将临时存储在第二缓冲器中的多个有效数据编程到第一存储平面中。

公开(公告)号：US09195539B2

公开(公告)日：2015-11-24

申请号：US13943755

申请日：2013-07-16

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Zhen-U Liu

IPC: G11C29/00 ,  G06F11/10 ,  G11B20/18 ,  H03M13/29 ,  H03M13/27

CPC classification number: G06F11/1068 ,  G06F11/1008 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1076 ,  G11B20/1833 ,  H03M13/27 ,  H03M13/29

Abstract: A method for reading data from a block of a flash memory is provided, where the block includes a plurality of pages and at least one parity page, each of the pages includes a plurality of sectors used for storing data and associated row parities, each of the sectors of the parity page is used to store a column parity. The method includes: reading data from a specific page of the pages; decoding the data of the specific page; and when a specific sector of the specific page fails to be decoded, sequentially reading all original data of the pages and the parity page, and performing error correction upon the specific sector according to at least a portion of the original data of the pages and the parity page corresponding to the specific sector.

Abstract translation: 提供了一种从闪速存储器块读取数据的方法，其中该块包括多个页面和至少一个奇偶校验页面，每个页面包括用于存储数据和相关行行奇偶校验的多个扇区，每个扇区 奇偶校验页面的扇区用于存储列奇偶校验。 该方法包括：从页面的特定页面读取数据; 解码特定页面的数据; 并且当特定页面的特定扇区不能被解码时，顺序地读取页面和奇偶校验页面的所有原始数据，并且根据页面的原始数据的至少一部分和特定扇区执行错误校正，并且 对应于特定扇区的奇偶校验页。

公开(公告)号：US20150135034A1

公开(公告)日：2015-05-14

申请号：US14600020

申请日：2015-01-20

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/56

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C2211/5641

Abstract: A memory control method is used for controlling a flash memory. The flash memory includes a first memory element and a second memory element. The second memory element includes multiple blocks and each block includes multiple pages. In this method, original data are written to the first memory element. Input data are obtained by reading the original data from the first memory element. The input data includes multiple input data rows. The input data rows are divided into data groups. Each input data row corresponding to each data row is written to a corresponding data page on the second memory element. A parity row corresponding to each data group is written to a data page on the second memory element. The number of data rows for each data group is smaller than the number of each block in the second memory element.

Abstract translation: 存储器控制方法用于控制闪速存储器。 闪速存储器包括第一存储器元件和第二存储器元件。 第二存储器元件包括多个块，并且每个块包括多个页。 在该方法中，将原始数据写入第一存储元件。 通过从第一存储元件读取原始数据来获得输入数据。 输入数据包括多个输入数据行。 输入数据行分为数据组。 对应于每个数据行的每个输入数据行被写入到第二存储器元件上的对应的数据页。 对应于每个数据组的奇偶校验行被写入第二存储器元件上的数据页。 每个数据组的数据行数小于第二个存储器元件中每个块的数量。

公开(公告)号：US20140189222A1

公开(公告)日：2014-07-03

申请号：US14197175

申请日：2014-03-04

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26

Abstract: A method for performing data shaping is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: performing a program optimization operation according to original data and a plurality of shaping codes, in order to generate trace back information corresponding to a Trellis diagram and utilize the trace back information as side information; and dynamically selecting at least one shaping code from the shaping codes according to the side information to perform data shaping on the original data.

Abstract translation: 一种用于执行数据整形的方法被应用于闪速存储器的控制器，其中闪速存储器包括多个块。 该方法包括：根据原始数据和多个整形代码执行程序优化操作，以便产生对应于网格图的追溯信息，并利用回溯信息作为辅助信息; 并且根据侧信息动态地从整形码中选择至少一个整形码，以对原始数据执行数据整形。

公开(公告)号：US20140146615A1

公开(公告)日：2014-05-29

申请号：US14171207

申请日：2014-02-03

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/26 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/3431

Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.

Abstract translation: 一种用于读取存储在闪速存储器中的数据的方法。 闪速存储器包括多个存储单元，并且每个存储单元具有特定的阈值电压。 该方法包括：获得表示第一组存储器单元的阈值电压的第一阈值电压分布; 获得表示第二组存储器单元的阈值电压的第二阈值电压分布，其中第二阈值电压分布不同于第一阈值电压分布，并且第一组存储器单元包括第二组的至少一部分 的记忆细胞; 以及控制所述闪速存储器，以根据所述第二阈值电压分布对所述第一组存储器单元执行至少一次读操作。

公开(公告)号：US20130332801A1

公开(公告)日：2013-12-12

申请号：US13912215

申请日：2013-06-07

Applicant: Silicon Motion Inc.

Inventor： Chen-Yu Weng ,  Tsung-Chieh Yang

IPC: G06F11/10 ,  G06F12/02

CPC classification number: G06F11/1008 ,  G06F11/1048 ,  G06F12/0246 ,  G11C16/3404 ,  G11C16/3418 ,  G11C2029/0411

Abstract: A method for correcting data bit of at least a cell of a flash memory includes: determining a contributing factor of level distribution corresponding to an electric level of a first cell to generate a first determination result; and, correcting/modifying the data bit corresponding to the electric potential of the first cell according to the first determination result.

Abstract translation: 用于校正闪速存储器的至少单元的数据位的方法包括：确定与第一单元电平相对应的电平分布的贡献因子以产生第一确定结果; 以及根据第一确定结果校正/修改对应于第一单元电位的数据位。

公开(公告)号：US20130329492A1

公开(公告)日：2013-12-12

申请号：US13911096

申请日：2013-06-06

Applicant: SILICON MOTION INC.

Inventor： Tsung-Chieh Yang

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C2211/5641

Abstract: A memory control method is used for controlling a flash memory. The flash memory includes a first memory element and a second memory element. The second memory element includes multiple blocks and each block includes multiple pages. In this method, original data are written to the first memory element. Input data are obtained by reading the original data from the first memory element. The input data includes multiple input data rows. The input data rows are divided into data groups. Each input data row corresponding to each data row is written to a corresponding data page on the second memory element. A parity row corresponding to each data group is written to a data page on the second memory element. The number of data rows for each data group is smaller than the number of each block in the second memory element.

公开(公告)号：US20130304977A1

公开(公告)日：2013-11-14

申请号：US13944866

申请日：2013-07-17

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hsiao-Te Chang ,  Wen-Long Wang

IPC: G06F3/06

CPC classification number: G11C11/5642 ,  G06F3/0604 ,  G06F3/0622 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0679 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/26

Abstract: A method for performing memory access management includes: with regard to a same Flash cell of a Flash memory, receiving a first digital value outputted by the Flash memory, requesting the Flash memory to output at least one second digital value, wherein the first digital value and the at least one second digital value are utilized for determining information of a same bit stored in the Flash cell, and a number of various possible states of the Flash cell correspond to a possible number of bit(s) stored in the Flash cell; based upon the second digital value, generating/obtaining soft information of the Flash cell, for use of performing soft decoding; and controlling the Flash memory to perform sensing operations by respectively utilizing a plurality of sensing voltages that are not all the same, in order to generate the first digital value and the second digital value.

Abstract translation: 一种用于执行存储器存取管理的方法包括：关于闪速存储器的相同闪存单元，接收闪速存储器输出的第一数字值，请求闪速存储器输出至少一个第二数字值，其中第一数字值 并且所述至少一个第二数字值用于确定存储在所述闪存单元中的相同位的信息，并且所述闪存单元的多个可能状态的数量对应于所述闪存单元中存储的可能数量的位; 基于所述第二数字值，生成/获取所述闪存单元的软信息，以用于执行软解码; 以及通过分别利用不完全相同的多个感测电压来控制闪存以执行感测操作，以便产生第一数字值和第二数字值。

公开(公告)号：US12277966B2

公开(公告)日：2025-04-15

申请号：US18522128

申请日：2023-11-28

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Hsiao-Te Chang ,  Wen-Long Wang

IPC: G11C11/56 ,  G06F3/06 ,  G11C16/08 ,  G11C16/26

Abstract: A method for performing memory access of a Flash cell of a Flash memory includes: performing a series of sensing operations respectively corresponding to a plurality of sensing voltages, wherein a sensing voltage of a specific sensing operation of the series of sensing operations has a sensing voltage determined according to a result of an initial sensing operation of the series of sensing operations; determining a threshold voltage of the Flash cell according to at least a digital value generated by the series of sensing operations; and using the determined threshold voltage to perform soft decoding of the Flash cell.