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    System And Method For Managing Peak Power Demand And Noise In Non-volatile Memory Array
    213.
    发明申请
    System And Method For Managing Peak Power Demand And Noise In Non-volatile Memory Array 审中-公开

    公开(公告)号：US20190295647A1

    公开(公告)日：2019-09-26

    申请号：US16015020

    申请日：2018-06-21

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Vipin Tiwari ,  Hieu Van Tran ,  Nhan Do ,  Mark Reiten

    IPC: G11C16/04 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11521

    Abstract: A memory device includes rows and columns of memory cells, word lines each connected to a memory cell row, bit lines each connected to a memory cell column, a word line driver connected to the word lines, a bit line driver connected to the bit lines, word line switches each disposed on one of the word lines for selectively connecting one memory cell row to the word line driver, and bit line switches each disposed on one of the bit lines for selectively connecting one memory cell column to the bit line driver. A controller controls the word line switches to connect only some of the rows of memory cells to the word line driver at a first point in time, and controls the bit line switches to connect only some of the columns of memory cells to the bit line driver at a second point in time.

    Twin Bit Non-volatile Memory Cells With Floating Gates In Substrate Trenches
    214.
    发明申请
    Twin Bit Non-volatile Memory Cells With Floating Gates In Substrate Trenches 审中-公开

    公开(公告)号：US20190214396A1

    公开(公告)日：2019-07-11

    申请号：US16160812

    申请日：2018-10-15

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chunming Wang ,  Andy Liu ,  Xian Liu ,  Leo Xing ,  Melvin Diao ,  Nhan Do

    IPC: H01L27/11521

    Abstract: A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.

    High Density Split-Gate Memory Cell
    216.
    发明申请
    High Density Split-Gate Memory Cell 审中-公开

    公开(公告)号：US20190172529A1

    公开(公告)日：2019-06-06

    申请号：US16273337

    申请日：2019-02-12

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  XIAN LIU ,  VIPIN TIWARI ,  HIEU VAN TRAN

    IPC: G11C11/419 ,  H01L29/788 ,  H01L29/66 ,  G11C16/14 ,  G11C16/04 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11521

    Abstract: A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.

    System And Method For Storing Multibit Data In Non-volatile Memory
    217.
    发明申请
    System And Method For Storing Multibit Data In Non-volatile Memory 审中-公开

    公开(公告)号：US20190139602A1

    公开(公告)日：2019-05-09

    申请号：US16148304

    申请日：2018-10-01

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Vipin Tiwari ,  Nhan Do ,  Hieu Van Tran

    IPC: G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

    Abstract: A method of reading a memory device having a plurality of memory cells by, and a device configured for, reading a first memory cell of the plurality of memory cells to generate a first read current, reading a second memory cell of the plurality of memory cells to generate a second read current, applying a first offset value to the second read current, and then combining the first and second read currents to form a third read current, and then determining a program state using the third read current. Alternately, a first voltage is generated from the first read current, a second voltage is generated from the second read current, whereby the offset value is applied to the second voltage, wherein the first and second voltages are combined to form a third voltage, and then the program state is determined using the third voltage.

    METHOD OF FORMING SPLIT-GATE, TWIN-BIT NON-VOLATILE MEMORY CELL
    219.
    发明申请
    METHOD OF FORMING SPLIT-GATE, TWIN-BIT NON-VOLATILE MEMORY CELL 审中-公开

    公开(公告)号：US20180226421A1

    公开(公告)日：2018-08-09

    申请号：US15945659

    申请日：2018-04-04

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chunming Wang ,  Nhan Do

    IPC: H01L27/11521 ,  G11C16/04 ,  H01L29/423 ,  G11C16/10 ,  G11C16/16

    CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328

    Abstract: A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region adjacent to the first region. A second floating gate is disposed over and insulated from a second portion of the channel region adjacent to the second region. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. A first erase gate disposed over and insulated from the first region. A second erase gate disposed is over and insulated from the second region.

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