公开(公告)号：US11916133B2

公开(公告)日：2024-02-27

申请号：US17676699

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/768

CPC classification number: H01L29/6656 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/66545

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

公开(公告)号：US11910617B2

公开(公告)日：2024-02-20

申请号：US17098919

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin

IPC: H10B51/30 ,  H01L29/66 ,  H01L29/786 ,  H10B51/20

CPC classification number: H10B51/30 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  H10B51/20

Abstract: Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.

公开(公告)号：US11903221B2

公开(公告)日：2024-02-13

申请号：US17156320

申请日：2021-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chenchen Wang ,  Chun-Chieh Lu ,  Chi On Chui ,  Yu-Ming Lin ,  Sai-Hooi Yeong

IPC: H10B63/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B61/00

CPC classification number: H10B63/84 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78642 ,  H10B61/22 ,  H10B63/34

Abstract: A device includes a first transistor over a substrate, a second transistor disposed over the first transistor, and a memory element disposed over the second transistor. The second transistor includes a channel layer, a gate dielectric layer surrounding a sidewall of the channel layer, and a gate electrode surrounding a sidewall of the gate dielectric layer.

公开(公告)号：US11903189B2

公开(公告)日：2024-02-13

申请号：US16924903

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chih-Yu Chang ,  Han-Jong Chia ,  Chenchen Jacob Wang ,  Yu-Ming Lin

IPC: H10B41/27 ,  H01L29/06 ,  H01L29/423 ,  H10B41/30 ,  G11C16/24 ,  G11C16/08

CPC classification number: H10B41/27 ,  G11C16/08 ,  G11C16/24 ,  H01L29/0669 ,  H01L29/42392 ,  H10B41/30

Abstract: Three-dimensional memories are provided. A three-dimensional memory includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines and a plurality of source lines. The memory cells are divided into a plurality of groups, and the groups of memory cells are formed in respective levels stacked along a first direction. The word lines extend along a second direction, and the second direction is perpendicular to the first direction. Each of the bit lines includes a plurality of sub-bit lines formed in the respective levels. Each of the source lines includes a plurality of sub-source lines formed in respective levels. In each of the levels, the memory cells of the corresponding group are arranged in a plurality of columns, and the sub-bit lines and the sub-source lines are alternately arranged between two adjacent columns.

公开(公告)号：US20240021707A1

公开(公告)日：2024-01-18

申请号：US18364574

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/768

CPC classification number: H01L29/6656 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/66545

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

公开(公告)号：US11855208B2

公开(公告)日：2023-12-26

申请号：US16898659

申请日：2020-06-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung Tsai ,  Shahaji B. More ,  Cheng-Yi Peng ,  Yu-Ming Lin ,  Kuo-Feng Yu ,  Ziwei Fang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66 ,  H01L21/027 ,  H01L29/161 ,  H01L29/36 ,  H01L29/165 ,  H01L21/3105

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L21/0274 ,  H01L21/31053 ,  H01L29/161 ,  H01L29/36

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a fin structure extended above a substrate and forming a gate structure formed over a portion of the fin structure. The method also includes forming a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The method further includes doping an outer portion of the S/D structure to form a doped region, and the doped region includes gallium (Ga). The method includes forming a metal silicide layer over the doped region; and forming an S/D contact structure over the metal silicide layer.

公开(公告)号：US20230413544A1

公开(公告)日：2023-12-21

申请号：US18362092

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chun-Chieh Lu ,  Yu-Ming Lin

IPC: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C7/18 ,  H10B43/27 ,  H10B41/10 ,  H10B43/10 ,  G11C8/14

Abstract: In an embodiment, a method includes forming a multi-layer stack including alternating layers of an isolation material and a semiconductor material, patterning the multi-layer stack to form a first channel structure in a first region of the multi-layer stack, where the first channel structure includes the semiconductor material, depositing a memory film layer over the first channel structure, etching a first trench extending through a second region of the multi-layer stack to form a first dummy bit line and a first dummy source line in the second region, where the first dummy bit line and first dummy source line each include the semiconductor material, and replacing the semiconductor material of the first dummy bit line and the first dummy source line with a conductive material to form a first bit line and a first source line.

公开(公告)号：US20230389336A1

公开(公告)日：2023-11-30

申请号：US18446586

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chenchen Jacob Wang ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chi On Chui

IPC: H10B61/00 ,  H01L21/02 ,  H01L29/24 ,  H10N50/01

CPC classification number: H10B61/22 ,  H01L21/02565 ,  H01L29/24 ,  H10N50/01

Abstract: In an embodiment, a semiconductor device includes a first dielectric layer over a substrate and a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each including a bottom electrode in the first dielectric layer, a conductive gate in a second dielectric layer, where the second dielectric layer is over the bottom electrode and the first dielectric layer, a channel region extending through the conductive gate to contact the bottom electrode, and a top electrode over the channel region.

公开(公告)号：US11804486B2

公开(公告)日：2023-10-31

申请号：US17572212

申请日：2022-01-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Huan-Chieh Su ,  Li-Zhen Yu ,  Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/027 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/0274 ,  H01L21/3086 ,  H01L21/30604

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

公开(公告)号：US11799030B2

公开(公告)日：2023-10-24

申请号：US17811212

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Chang ,  Lin-Yu Huang ,  Han-Jong Chia ,  Bo-Feng Young ,  Yu-Ming Lin

IPC: H01L29/78 ,  H01L29/40 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/78391 ,  H01L29/40111 ,  H01L29/516

Abstract: A device includes a substrate, gate stacks, source/drain (S/D) features over the substrate, S/D contacts over the S/D features, and one or more dielectric layers over the gate stacks and the S/D contacts. A via structure penetrates the one or more dielectric layers and electrically contacts one of the gate stacks and the S/D contacts. And a ferroelectric (FE) stack is over the via structure and directly contacting the via structure, wherein the FE stack includes an FE feature and a top electrode over the FE feature.