公开(公告)号：US09627379B1

公开(公告)日：2017-04-18

申请号：US15062219

申请日：2016-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/82 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823456 ,  H01L29/0657 ,  H01L29/66545

Abstract: FinFET devices and methods of forming the same are disclosed. One FinFET device includes a substrate with first and second fins in a first region and third and fourth fins in a second region, and first to fourth gates respectively across the first to fourth fins. The first end sidewall of the first gate is faced to the second end sidewall of the second gate, and a first opening is formed between the first and second end sidewalls. The third end sidewall of the third gate is faced to the fourth end sidewall of the fourth gate, and a second opening is formed between the third and fourth end sidewalls. The first and second regions have different pattern densities, and the included angle between the sidewall of the first opening and the substrate is different from the included angle between the sidewall of the second opening and the substrate.

公开(公告)号：US09620417B2

公开(公告)日：2017-04-11

申请号：US14502784

申请日：2014-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin Chen ,  Tung-Wen Cheng ,  Che-Cheng Chang ,  Jr-Jung Lin ,  Chih-Han Lin

IPC: H01L21/8234 ,  H01L21/3213 ,  H01J37/32

CPC classification number: H01J37/32449 ,  H01J2237/334 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/67069 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481

Abstract: A method of manufacturing a Fin-FET device includes forming a plurality of fins in a substrate, which the substrate includes a center region and a periphery region surrounding the center region. A gate material layer is deposited over the fins, and the gate material layer is etched with an etching gas to form gates, which the etching gas is supplied at a ratio of a flow rate at the center region to a flow rate at the periphery region in a range from 0.33 to 3.

公开(公告)号：US09590032B2

公开(公告)日：2017-03-07

申请号：US14569336

申请日：2014-12-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Han Lin ,  Jr-Jung Lin ,  Ming-Ching Chang

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0642 ,  H01L21/76224 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-like field-effect transistor (Fin-FET) device includes a substrate, a fin structure disposed on the substrate, and an isolation structure disposed adjacent to the fin structure. The fin structure includes a recessed structure, which a bottom of the recessed structure is below a top surface of the isolation structure.

Abstract translation: 鳍状场效应晶体管（Fin-FET）器件包括衬底，设置在衬底上的鳍结构以及邻近翅片结构设置的隔离结构。 翅片结构包括凹陷结构，凹陷结构的底部在隔离结构的顶表面下方。

公开(公告)号：US09570567B1

公开(公告)日：2017-02-14

申请号：US14984514

申请日：2015-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L21/02068 ,  H01L21/30604 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET includes a substrate, a fin structure, a dielectric layer, a metal gate, two spacers, a source and a drain. The fin structure is disposed on the substrate. The dielectric layer is disposed on the fin structure and covers two opposite side surfaces of the fin structure. The dielectric layer includes two first portions protruding from the side surfaces of the fin structure, such that two opposite first recesses are formed in the dielectric layer. The metal gate is disposed on a second portion of the dielectric layer which is sandwiched between the first portions. The spacers are disposed on the first portions of the dielectric layer and protrude from the first portions of the dielectric layer respectively, such that two second recesses are formed in the spacers. The source and drain are respectively disposed in the first recesses and the second recesses on the substrate.

Abstract translation: FinFET包括衬底，鳍结构，电介质层，金属栅极，两个间隔物，源极和漏极。 翅片结构设置在基板上。 电介质层设置在翅片结构上并且覆盖翅片结构的两个相对的侧表面。 电介质层包括从翅片结构的侧表面突出的两个第一部分，使得在电介质层中形成两个相对的第一凹部。 金属栅极设置在夹在第一部分之间的电介质层的第二部分上。 间隔物设置在电介质层的第一部分上，并且从电介质层的第一部分突出，使得在间隔物中形成两个第二凹槽。 源极和漏极分别设置在基板的第一凹部和第二凹部中。

公开(公告)号：US09508719B2

公开(公告)日：2016-11-29

申请号：US14554682

申请日：2014-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin Chen ,  Tung-Wen Cheng ,  Che-Cheng Chang ,  Chun-Lung Ni ,  Jr-Jung Lin ,  Chih-Han Lin

IPC: H01L27/092 ,  H01L27/088 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L21/033 ,  H01L21/3213

CPC classification number: H01L21/0338 ,  H01L21/0206 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure is provided. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure further includes an inter-layer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 20 nm to about 40 nm.

Abstract translation: 提供了一种用于形成FinFET器件结构的鳍式场效应晶体管（FinFET）器件结构和方法。 FinFET器件结构包括衬底和在衬底上方延伸的第一鳍结构和第二鳍结构。 FinFET器件结构还包括形成在第一鳍结构上的第一晶体管和形成在第二鳍结构上的第二晶体管。 FinFET器件结构还包括形成在第一晶体管和第二晶体管之间的端到端间隙中的层间电介质（ILD）结构，并且端对端间隙具有在约20° nm至约40nm。

公开(公告)号：US09450099B1

公开(公告)日：2016-09-20

申请号：US14743768

申请日：2015-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Chen-Hsiang Lu ,  Wei-Ting Chen ,  Yu-Cheng Liu

IPC: H01L21/70 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/6653 ,  H01L21/28008 ,  H01L21/28247 ,  H01L21/31116 ,  H01L23/5226 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a protection element over the gate stack. The protection element has an upper portion and a lower portion between the upper portion and the gate stack, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a side surface of the protection element and a sidewall of the gate stack. The semiconductor device structure further includes a conductive contact electrically connected to a conductive feature over the semiconductor substrate.

Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括半导体衬底上的栅极堆叠以及栅堆叠上的保护元件。 保护元件在上部和栅极堆叠之间具有上部和下部，并且上部比下部更宽。 半导体器件结构还包括在保护元件的侧表面上的间隔元件和栅极堆叠的侧壁。 半导体器件结构还包括电连接到半导体衬底上的导电特征的导电接触。

公开(公告)号：US09401415B2

公开(公告)日：2016-07-26

申请号：US14181320

申请日：2014-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chang-Yin Chen ,  Jr-Jung Lin ,  Chih-Han Lin ,  Yung-Jung Chang

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. The FinFET device structure includes a fin structure extending above a substrate and a gate dielectric layer formed over the fin structure. The FinFET device structure also includes a gate electrode formed on the gate dielectric layer. The FinFET device structure further includes a number of gate spacers formed on sidewalls of the gate electrode. The gate spacers are in direct contact with the fin structure.

Abstract translation: 提供了用于形成鳍状场效应晶体管（FinFET）器件结构的实施例。 FinFET器件结构包括在衬底上延伸的翅片结构和形成在鳍结构上的栅极电介质层。 FinFET器件结构还包括形成在栅极介电层上的栅电极。 FinFET器件结构还包括形成在栅电极的侧壁上的多个栅极间隔物。 栅极间隔件与翅片结构直接接触。

公开(公告)号：US12294023B2

公开(公告)日：2025-05-06

申请号：US17818647

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Ping Chen ,  Kuei-Yu Kao ,  Shih-Yao Lin ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78

Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.

公开(公告)号：US20240421211A1

公开(公告)日：2024-12-19

申请号：US18783711

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Shu-Yuan Ku

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.

公开(公告)号：US12142655B2

公开(公告)日：2024-11-12

申请号：US17336599

申请日：2021-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chen-Ping Chen ,  Hsiaowen Lee ,  Chih-Han Lin

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

Abstract: In an embodiment, a device includes: an isolation region; nanostructures protruding above a top surface of the isolation region; a gate structure wrapped around the nanostructures, the gate structure having a bottom surface contacting the isolation region, the bottom surface of the gate structure extending away from the nanostructures a first distance, the gate structure having a sidewall disposed a second distance from the nanostructures, the first distance less than or equal to the second distance; and a hybrid fin on the sidewall of the gate structure.