公开(公告)号：US11803311B2

公开(公告)日：2023-10-31

申请号：US17218700

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Johnathan Alsop ,  Nuwan Jayasena ,  Shaizeen Aga ,  Andrew McCrabb

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods and apparatuses to control digital data transfer via a memory channel between a memory module and a processor are disclosed. At least one of the memory module or the processor coalesces a plurality of short data words into multicast coalesced block data comprising a single data block for transfer via the memory channel. Each of the plurality of short data words pertains to one of at least two partitioned memory submodules in the memory module. The multicast coalesced block data is communicated over the memory channel.

公开(公告)号：US20230342528A1

公开(公告)日：2023-10-26

申请号：US17990005

申请日：2022-11-18

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： David Akselrod ,  Shi Han Zhang ,  Chun Fung Lam

IPC: G06F30/3308 ,  G06F30/3323 ,  G06N20/00

CPC classification number: G06F30/3308 ,  G06F30/3323 ,  G06N20/00

Abstract: Techniques for implementing a mixed signal feedback design for verification that reduce production and verification time by enabling piecemeal verification of components of a circuit design selectively, accurately, and exhaustively before a final, overall circuit design is completed are disclosed. Circuit nodes in an emulation model are selected and mixed signal feedback is provided to the nodes in response to signals detected at the nodes such that behavior of unavailable or unverified components to be located at the nodes can be simulated. Mixed signal feedback can be provided to the node to enable verification of the emulation model without having to wait for the unverified or unavailable components to be provided or verified. A request for manufacture may be generated including aspects of the emulation model to enable verification of a fabricated circuit in a similar or identical manner to those used to verify the emulation model.

公开(公告)号：US20230342325A1

公开(公告)日：2023-10-26

申请号：US18216908

申请日：2023-06-30

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gordon Caruk ,  Maurice B. Steinman ,  Gerald R. Talbot ,  Joseph D. Macri

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4282 ,  G06F13/1689 ,  G06F2213/0026

Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a non-PCIe protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a non-PCIe format, encapsulating the non-PCIe format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.

公开(公告)号：US11797369B2

公开(公告)日：2023-10-24

申请号：US17864804

申请日：2022-07-14

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Vilas Sridharan

IPC: G06F11/07 ,  G06F3/06 ,  G06F11/14

CPC classification number: G06F11/0772 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/141

Abstract: A memory controller includes a memory channel controller adapted to receive memory access requests and dispatch associated commands addressable in a system memory address space to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller number of virtual error types for reporting to an error monitoring module of a host operating system, the mapping based at least on a classification that the error condition will or will not have a deleterious effect on an executable process running on the host operating system.

公开(公告)号：US20230315171A1

公开(公告)日：2023-10-05

申请号：US17704912

申请日：2022-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Jerry Anton Ahrens ,  William Robert Alverson ,  Amitabh Mehra ,  Grant Evan Ley ,  Anil Harwani ,  Joshua Taylor Knight

IPC: G06F1/20 ,  H05K5/02 ,  H05K7/20

CPC classification number: G06F1/206 ,  H05K5/0213 ,  H05K5/0239 ,  H05K7/20209

Abstract: Package lids with carveouts configured for processor connection and alignment are described. Lid carveouts are configured to align and mechanically secure a cooling device to the package lid by receiving protrusions of the cooling device. Because the lid carveouts ensure precise alignment and orientation of a cooling device relative to a package lid, the lid design enables targeted cooling of discrete portions of the lid. Lid carveouts are further configured to expose one or more connectors disposed on a surface that supports package internal components. When contacted by corresponding connectors of a cooling device, the lid carveouts enable direct connections between the package and the attached cooling device. By creating a direct connection between package components and an attached cooling device, the lid carveouts enable a high-speed connection for proactive and on-demand cooling actuation.

公开(公告)号：US20230310995A1

公开(公告)日：2023-10-05

申请号：US17709904

申请日：2022-03-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Mehdi Saeedi ,  Ian Charles Colbert ,  Thomas Daniel Perry ,  Gabor Sines

IPC: A63F13/56

CPC classification number: A63F13/56

Abstract: Systems, apparatuses, and methods for detecting personal-space violations in artificial intelligence (AI) based non-player characters (NPCs) are disclosed. An AI engine creates a NPC that accompanies and/or interacts with a player controlled by a user playing a video game. During gameplay, measures of context-dependent personal space around the player and/or one or more NPCs are generated. A control circuit monitors the movements of the NPC during gameplay and determines whether the NPC is adhering to or violating the measures of context-dependent personal space. The control circuit can monitor the movements of multiple NPCs simultaneously during gameplay, keeping a separate score for each NPC. After some amount of time has elapsed, the scores of the NPCs are recorded, and then the scores are provided to a machine learning engine to retrain the AI engines controlling the NPCs.

公开(公告)号：US11778803B2

公开(公告)日：2023-10-03

申请号：US17489252

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: G11C7/10 ,  H10B10/00 ,  H01L29/423

CPC classification number: H10B10/12 ,  G11C7/1045 ,  H01L29/42392

Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, a memory bit cell uses Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. The memory bit cell includes one of a read bit line and a write word line routed in no other metal layer other than a local interconnect layer. In addition, a six transistor (6T) random access data storage of the given memory bit cell consumes a planar area above a silicon substrate of four transistors.

公开(公告)号：US11776599B2

公开(公告)日：2023-10-03

申请号：US17485178

申请日：2021-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Patrick J. Shyvers

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/106 ,  G11C7/1039 ,  G11C7/1087

Abstract: A processing device is provided which includes a processor and a data storage structure. The data storage structure comprises a data storage array comprising a plurality of lines. Each line comprises at least one A latch configured to store a data bit and a clock gater. The data storage structure also comprises a write data B latch configured to store, over different clock cycles, a different data bit, each to be written to the at least one A latch of one of the plurality of lines. The data storage structure also comprises a plurality of write index B latches shared by the clock gaters of the lines. The write index B latches are configured to store, over the different clock cycles, combinations of index bits having values which index one of the lines to which a corresponding data bit is to be stored.

公开(公告)号：US20230307405A1

公开(公告)日：2023-09-28

申请号：US17656539

申请日：2022-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Lei Fu ,  Raja Swaminathan ,  Brett P. Wilkerson

IPC: H01L23/00

CPC classification number: H01L24/24 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/16 ,  H01L24/73 ,  H01L2924/37001 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1427 ,  H01L2924/14252 ,  H01L2224/215 ,  H01L2224/24137 ,  H01L2224/24101 ,  H01L2224/25175 ,  H01L2224/73209 ,  H01L2224/16137 ,  H01L25/0655

Abstract: An electronic device can include a first die, a second die, and an interconnect. The first die or the second die has a principal function as a power module or a memory. The first die includes a first bond pad, and the second die includes a second bond pad. The device sides of the first and second dies are along the same sides as the first and second bond pads. In an embodiment, the first die and the second die are in a chip first, die face-up configuration. The first and the second bond pads are electrically connected along a first solderless connection that includes the interconnect. In another embodiment, each material within the electrical connection between the first and the second bond pads has a flow point or melting point temperature of at least 300° C.

公开(公告)号：US11768778B2

公开(公告)日：2023-09-26

申请号：US17490820

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/00 ,  G06F12/123

CPC classification number: G06F12/123 ,  G06F2212/1044

Abstract: Techniques for performing cache operations are provided. The techniques include tracking re-references for cache lines of a cache, detecting that eviction is to occur, and selecting a cache line for eviction from the cache based on a re-reference indication.