公开(公告)号：US20240077522A1

公开(公告)日：2024-03-07

申请号：US18355977

申请日：2023-07-20

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Christophe Lorin ,  Nathalie Dubois

IPC: G01R19/165 ,  G01R15/04

CPC classification number: G01R19/16576 ,  G01R15/04

Abstract: A voltage matching circuit receives a first voltage received by a connector, and outputs a second voltage. The second voltage is equal to the first voltage, if the first voltage is less than a threshold voltage. The second voltage is equal to the first voltage divided by a first factor, if the first voltage is greater than or equal to the threshold voltage.

公开(公告)号：US11916480B2

公开(公告)日：2024-02-27

申请号：US17495306

申请日：2021-10-06

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Vincent Pinon

IPC: H02M3/158 ,  H02M1/08 ,  H02M1/00

CPC classification number: H02M3/158 ,  H02M1/08 ,  H02M1/0045

Abstract: In an embodiment, A switched-mode power supply includes: a first node; a second node configured to receive a DC input voltage; a third node configured to receive a reference voltage; first and second switching transistors; a first circuit configured to control the first switching transistor; and a second circuit configured to control the second switching transistor, wherein the switched-mode power supply is configured to deliver a regulated output voltage at the first node from the DC input voltage, and wherein the first and second circuits are configured to be powered from the output voltage.

公开(公告)号：US20240064427A1

公开(公告)日：2024-02-22

申请号：US18500449

申请日：2023-11-02

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Laurent Simony

IPC: H04N25/709 ,  H04N25/77 ,  H02M3/155

CPC classification number: H04N25/709 ,  H04N25/77 ,  H02M3/155

Abstract: In accordance with an embodiment, a power supply circuit includes: a first transistor device comprising a first gate associated with a first transconductance and a second gate associated with a transconductance greater than the first transconductance; and a second transistor device including a third gate associated with a second transconductance and a fourth gate associated with a transconductance greater than the second transconductance. The second transistor device is configured to supply power to at least one load, the first and the third gates are controlled by a closed regulation loop, and the second and the fourth gates are controlled by a sampled reference voltage.

公开(公告)号：US11889594B2

公开(公告)日：2024-01-30

申请号：US17654532

申请日：2022-03-11

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

Inventor： Manuel Gaertner ,  Philippe Sirito-Olivier ,  Giovanni Luca Torrisi ,  Thomas Urbitsch ,  Christophe Roussel ,  Fritz Burkhardt

IPC: H05B45/14 ,  H05B45/46 ,  H05B45/50 ,  H05B45/325

CPC classification number: H05B45/46 ,  H05B45/14 ,  H05B45/325 ,  H05B45/50

Abstract: A system includes lighting devices coupled to output supply pins, a microcontroller circuit, and a driver circuit, which receives data therefrom, and switches coupled in series to the lighting devices. The driver circuit includes output supply pins and selectively propagates a supply voltage to the output supply pins to provide respective pulse-width modulated supply signals at the output supply pins. The driver circuit computes duty-cycle values of the pulse-width modulated supply signals as a function of the data received from the microcontroller circuit. The lighting devices include at least one subset coupled to the same output supply pin. The microcontroller individually controls the switches via respective control signals to individually adjust a brightness of the lighting devices in the at least one subset of lighting devices.

公开(公告)号：US11889210B2

公开(公告)日：2024-01-30

申请号：US17575070

申请日：2022-01-13

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jerome Chossat ,  Mathieu Thivin

IPC: H04N25/68 ,  H04N25/772 ,  H04N25/702 ,  H04N25/76 ,  H04N25/683

CPC classification number: H04N25/68 ,  H04N25/772

Abstract: An electronic device includes a first array of image pixels having inputs coupled to first selection tracks and outputs coupled to first output tracks, a second array of test pixels having inputs coupled to second selection tracks and outputs coupled to the first output tracks, and a third array of test pixels having inputs coupled to the first selection tracks and outputs coupled to second output tracks. A processor is coupled to receive output signals on the first and second output tracks. The output signals from the test pixels of the second and third arrays are fixed at one or the other of only two values in the absence of a defect. The output signals received by the processor over the first and second output tracks are processed to determine presence or absence of a defect.

公开(公告)号：US11879909B2

公开(公告)日：2024-01-23

申请号：US17869301

申请日：2022-07-20

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Klodjan Bidaj ,  Benjamin Ardaillon ,  Lauriane Gateka

IPC: G01R31/00 ,  G01R31/26 ,  G01R31/28 ,  G01R1/02 ,  G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R1/18 ,  G01R1/24 ,  G01R1/28

CPC classification number: G01R1/0416 ,  G01R31/2808 ,  G01R31/2889

Abstract: A testing device for electronic dies includes a first support part and a second support part configured to be removably assembled with each other. The first and second support parts together define at least one housing where at least one electronic die can be arranged to be tested. The electronic die has a first surface with contacting elements. The at least one housing includes a first portion. This at least one housing is arranged to enable the at least one electronic die to occupy a first position in the housing where the first surface is spaced apart from the first portion, and is further arrange to enable the at least one electronic die to occupy a second position in the housing where the first surface bears against the first portion.

公开(公告)号：US11856307B2

公开(公告)日：2023-12-26

申请号：US18052478

申请日：2022-11-03

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Laurent Simony

IPC: H04N25/709 ,  H04N25/77 ,  H02M3/155 ,  G05F1/575 ,  H01L29/786 ,  H03M1/08

CPC classification number: H04N25/709 ,  H02M3/155 ,  H04N25/77

Abstract: In accordance with an embodiment, a power supply circuit includes: a first transistor device comprising a first gate associated with a first transconductance and a second gate associated with a transconductance greater than the first transconductance; and a second transistor device including a third gate associated with a second transconductance and a fourth gate associated with a transconductance greater than the second transconductance. The second transistor device is configured to supply power to at least one load, the first and the third gates are controlled by a closed regulation loop, and the second and the fourth gates are controlled by a sampled reference voltage.

公开(公告)号：US11853241B2

公开(公告)日：2023-12-26

申请号：US18065475

申请日：2022-12-13

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Jawad Benhammadi ,  Sylvain Meyer

IPC: G06F13/24 ,  G06F13/16 ,  G06F21/85 ,  H03K19/20 ,  G06F1/3237

CPC classification number: G06F13/24 ,  G06F1/3237 ,  G06F13/1689 ,  G06F21/85 ,  H03K19/20

Abstract: In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal likely to emanate from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.

公开(公告)号：US20230411271A1

公开(公告)日：2023-12-21

申请号：US18207954

申请日：2023-06-09

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Luc PETIT ,  Jerome LOPEZ ,  Karine SAXOD

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49827 ,  H01L23/3675 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/32245 ,  H01L24/32 ,  H01L2224/1413 ,  H01L2224/16225 ,  H01L24/73 ,  H01L2224/73253

Abstract: An electronic device includes an electronic chip located between a cover and an interconnection substrate. The electronic chip has contact pads located in front of a first surface of the interconnection substrate. At least one metal region (for example extending on the front surface) thermally couples at least one contact pad of the electronic chip to the cover.

公开(公告)号：US20230403791A1

公开(公告)日：2023-12-14

申请号：US18205655

申请日：2023-06-05

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain COFFY ,  Younes BOUTALEB

IPC: H05K1/03 ,  H05K1/11 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/036 ,  H05K1/11 ,  H05K1/0209 ,  H05K3/4697 ,  H05K2201/10689 ,  H05K2201/10121

Abstract: An integrated-circuit package includes a flexible electrical-connection element sandwiched between a first face of a first multilayer support substrate and a second face of a second multilayer support substrate. The flexible electrical-connection element laterally projects with respect to, and is in electrical contact with at least one of, the multilayer support substrates. The flexible electrical-connection element and the first multilayer support substrate include, at a first region, respectively two first mutually facing orifices defining together a first cavity. The first cavity is at least partially closed off by a first part of the second face of the second multilayer support substrate. A first component is located in the first cavity, attached at the first part of the second face of the second multilayer support substrate and in electrical contact with the flexible electrical-connection element through the second multilayer support substrate.