公开(公告)号：US20240395751A1

公开(公告)日：2024-11-28

申请号：US18788526

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Ying-Ju Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a redistribution structure, a first device and a second device attached to the redistribution structure, the first device including: a first die, a support substrate bonded to a first surface of the first die, and a second die bonded to a second surface of the first die opposite the first surface, where a total height of the first die and the second die is less than a first height of the second device, and where a top surface of the substrate is at least as high as a top surface of the second device, and an encapsulant over the redistribution structure and surrounding the first device and the second device.

公开(公告)号：US20240395728A1

公开(公告)日：2024-11-28

申请号：US18791100

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Te Huang ,  Hong-Wei Chan ,  Yung-Shih Cheng ,  Jiing-Feng Yang ,  Hui Lee

IPC: H01L23/544 ,  H01L21/768 ,  H01L23/522

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming an interconnect structure over a device wafer. The device wafer includes a first integrated circuit, a semiconductor substrate, and a redistribution structure. The method further includes forming a metallization layer and a group of dummy insertion structures having a stepped pattern density in a topmost dielectric layer of the interconnect structure. The group of dummy insertion structures and the metallization layer are planarized with the dielectric layer. The method further includes forming a first bonding layer over the group of dummy insertion structures, the metallization layer, and the dielectric layer. The method further includes bonding a carrier wafer to the first bonding layer, forming an opening through the semiconductor substrate, and forming a conductive via in the opening and electrically coupled to the redistribution structure.

公开(公告)号：US20240395683A1

公开(公告)日：2024-11-28

申请号：US18790830

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor device and method of manufacture is provided including a redistribution structure; a plurality of core substrates attached to the redistribution structure using conductive connectors, each core substrate of the plurality of core substrates comprising a plurality of conductive posts; and one or more molding layers encapsulating the plurality of core substrates, where the one or more molding layers extends along sidewalls of the plurality of core substrates, and where the one or more molding layers extends along a portion of a sidewall of each of the conductive posts.

公开(公告)号：US20240395623A1

公开(公告)日：2024-11-28

申请号：US18790968

申请日：2024-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Wei PENG ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L21/8234 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: A device includes first and second transistors, a conductive contact, a dielectric layer, and a conductive via. The first transistor includes a first gate, a first source/drain and a second source/drain at opposite sides of the first gate. The second transistor includes a second gate, a third source/drain and a fourth source/drain at opposite sides of the second gate. The conductive contact extends across the first source/drain and the third source/drain along a longitudinal direction of the first gate. The dielectric layer spaces apart the conductive contact from the first source/drain. The conductive via is in contact with the conductive contact. The conductive via vertically overlaps with the conductive contact and the dielectric layer.

公开(公告)号：US20240395617A1

公开(公告)日：2024-11-28

申请号：US18790994

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huei-Wen Hsieh ,  Kai-Shiang Kuo ,  Cheng-Hui Weng ,  Chun-Sheng Chen ,  Wen-Hsuan Chen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088

Abstract: A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer.

公开(公告)号：US20240395608A1

公开(公告)日：2024-11-28

申请号：US18791303

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao CHANG ,  Jia-Chuan YOU ,  Li-Zhen YU ,  Lin-Yu HUANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device with reduced contact resistance is provided. The semiconductor device includes a substrate having a channel region and a source/drain region, a source/drain contact structure over the source/drain region, a conductive structure over the source/drain contact structure, an interlayer dielectric (ILD) layer surrounding the conductive structure and source/drain contact structure, a dielectric liner between the ILD layer and the conductive structure, and a diffusion barrier between the dielectric liner and the conductive structure.

公开(公告)号：US20240395598A1

公开(公告)日：2024-11-28

申请号：US18760573

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang ,  Chun-Hung Lee

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

Abstract: A method for shallow trench isolation structures in a semiconductor device and a semiconductor device including the shallow trench isolation structures are disclosed. In an embodiment, the method may include forming a trench in a substrate; depositing a first dielectric liner in the trench; depositing a first shallow trench isolation (STI) material over the first dielectric liner, the first STI material being deposited as a conformal layer; etching the first STI material; depositing a second STI material over the first STI material, the second STI material being deposited as a flowable material; and planarizing the second STI material such that top surfaces of the second STI material are co-planar with top surfaces of the substrate.

公开(公告)号：US20240395581A1

公开(公告)日：2024-11-28

申请号：US18790913

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chih-Kai Yang ,  Chun-Liang Chen ,  Wei-Ting Chien ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/67 ,  G03F7/40

Abstract: In an embodiment, a pattern transfer processing chamber includes a pattern transfer processing chamber and a loading area external to the pattern transfer processing chamber. The loading area is configured to transfer a wafer to or from the pattern transfer processing chamber. The loading area comprises a first region including a loadport, a second region including a load-lock between the first region and the pattern transfer processing chamber, and an embedded baking chamber configured to heat a patterned photoresist on the wafer.

公开(公告)号：US20240395536A1

公开(公告)日：2024-11-28

申请号：US18790002

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang Hung ,  Huan-Just Lin ,  Sheng-Liang Pan ,  Yungtzu Chen ,  Po-Chuan Wang ,  Guan-Xuan Chen

IPC: H01L21/02 ,  H01L21/8234

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first opening through a dielectric layer, the first opening exposing a conductive region. A wet cleaning is used after the forming the first opening, and the first opening is treated after the wet cleaning the first opening, the treating the first opening comprising turning a sidewall treatment precursor and a bottom treatment precursor into a first plasma mixture, the sidewall treatment precursor being different from the bottom treatment precursor. The first opening is filled with a conductive material after the treating the first opening.

公开(公告)号：US20240394460A1

公开(公告)日：2024-11-28

申请号：US18790306

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin CHUANG ,  Shih-Yao LIN ,  Szu-ju HUANG ,  Yin-An CHEN ,  Shih Feng HONG

IPC: G06F30/398 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06N20/00

Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.