公开(公告)号：US20240057340A1

公开(公告)日：2024-02-15

申请号：US18491711

申请日：2023-10-20

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H10B43/40 ,  H01L23/00 ,  H01L23/532 ,  H01L23/522 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/40 ,  H01L24/05 ,  H01L23/53228 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H01L2224/05124 ,  H01L2224/05025

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure. The microelectronic device structure comprises a semiconductive base structure, and a memory array region vertically overlying the semiconductive base structure and comprising memory cells. The microelectronic device structure is attached to a base structure. A portion of the semiconductive base structure is removed after attaching the microelectronic device structure to a base structure. A control logic region is formed vertically over a remaining portion of the semiconductive base structure. The control logic region comprises control logic devices in electrical communication with the memory cells of the memory array region. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.

公开(公告)号：US20240055400A1

公开(公告)日：2024-02-15

申请号：US17884475

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Bret K. Street ,  Kyle K. Kirby ,  Wei Zhou ,  Thiagarajan Raman

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06582

Abstract: This document discloses techniques, apparatuses, and systems for providing a semiconductor device assembly with a substrate for vertically assembled semiconductor dies. A semiconductor assembly is described that includes a semiconductor die coupled to a substrate such that an active surface of the semiconductor die is substantially orthogonal to a top surface of the substrate. The substrate includes a surface having a recessed slot at which a side surface of the semiconductor die couples. The semiconductor die includes a contact pad that couples to a contact pad at the recessed slot. In doing so, the techniques, apparatuses, and systems herein enable a robust and cost-efficient semiconductor device to be assembled.

公开(公告)号：US20240014170A1

公开(公告)日：2024-01-11

申请号：US17857304

申请日：2022-07-05

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Akshay N. Singh ,  Kunal R. Parekh

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L25/18 ,  H01L24/05 ,  H01L24/06 ,  H01L25/50 ,  H01L24/08 ,  H01L24/32 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L24/96 ,  H01L2224/96 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/08145 ,  H01L24/92 ,  H01L2224/92125 ,  H01L2224/9222

Abstract: A semiconductor device assembly can include an assembly substrate having a top surface, a top semiconductor device having a bottom surface, and a plurality of intermediary semiconductor devices. Each of intermediary semiconductor device can be bonded to both the assembly substrate top surface and the top device bottom surface. Each intermediary semiconductor device can also include a semiconductor substrate, a memory array, a first bond pad, a second bond pad, and a conductive column. The first bond pad can electrically couple the assembly substrate to the intermediary semiconductor device; the second bond pad can electrically couple the top semiconductor device to the intermediary semiconductor device; and the conductive column can electrically couple the first bond pad to the second bond pad, and can be exclusive of any electrical connection to the memory array.

公开(公告)号：US20230413583A1

公开(公告)日：2023-12-21

申请号：US18460358

申请日：2023-09-01

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H10B63/00 ,  G11C5/06 ,  H01L25/16 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10N70/00

CPC classification number: H10B63/84 ,  G11C5/063 ,  H01L25/16 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35 ,  H10N70/882 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B63/34 ,  H10N70/011 ,  H10B41/41

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a first control logic region comprising first control logic devices, and a first memory array region vertically overlying the first control logic region and comprising an array of vertically extending strings of memory cells. An additional microelectronic device structure comprising a semiconductive material is attached to an upper surface of the microelectronic device structure. A portion of the semiconductive material is removed. A second control logic region is formed over the first memory array region. The second control logic region comprises second control logic devices and a remaining portion of the semiconductive material. A second memory array region is formed over the second control logic region. The second memory array region comprises an array of resistance variable memory cells. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US11842990B2

公开(公告)日：2023-12-12

申请号：US17364377

申请日：2021-06-30

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kunal R. Parekh

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H10B12/00

CPC classification number: H01L25/18 ,  H01L24/83 ,  H01L25/50 ,  H10B12/036 ,  H10B12/33 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488 ,  H01L2224/83895 ,  H01L2224/83896

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, word lines coupled to the memory cells, and isolation material overlying the memory cells, the digit lines, and the word lines. An additional microelectronic device structure assembly comprising control logic devices and additional isolation material overlying the control logic devices is formed. The additional isolation material of the additional microelectronic device structure assembly is bonded to the isolation material of the microelectronic device structure assembly to attach the additional microelectronic device structure assembly to the microelectronic device structure assembly. The memory cells are electrically connected to at least some of the control logic devices after bonding the additional isolation material to the isolation material. Microelectronic devices, electronic systems, and additional methods are also described.

公开(公告)号：US11817305B2

公开(公告)日：2023-11-14

申请号：US17325122

申请日：2021-05-19

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/48 ,  H01L23/00 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76877 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Systems and methods for a semiconductor device having a front-end-of-line structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor substrate material and a front side, and an interconnect structure extending through the dielectric material. The interconnect structure may be electrically connected to a semiconductor memory array proximate the front side of the dielectric material. The semiconductor device may further have an insulating material encasing at least a portion of the semiconductor memory array and an opening created during back-end-of-line processing through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.

公开(公告)号：US20230284465A1

公开(公告)日：2023-09-07

申请号：US18111287

申请日：2023-02-17

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Kunal R. Parekh

IPC: H10B80/00 ,  H01L23/48 ,  H01L23/00

CPC classification number: H10B80/00 ,  H01L23/481 ,  H01L24/08 ,  H01L24/94 ,  H01L24/80 ,  H01L2224/08146 ,  H01L2224/94 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L24/05 ,  H01L2224/80379

Abstract: Semiconductor die stacks and associated systems and methods are disclosed. In an embodiment, a semiconductor die stack corresponds to a pair of a logic die and a memory die directly bonded together. The logic die includes integrated circuits generated by relatively high temperature process steps whereas the memory die includes memory cells with materials generated using relatively low temperature process steps. A logic wafer including the logic dies and a memory wafer including the memory dies are separately fabricated. Subsequently, the logic wafer and the memory wafer are directly bonded to generate the semiconductor die stacks. Either the logic dies or the memory dies include through-substrate vias (TSVs) to provide power and signals for the semiconductor die stacks. The resulting semiconductor devices operate as a single device as if they were formed in a monolithic substrate.

公开(公告)号：US11751408B2

公开(公告)日：2023-09-05

申请号：US17165746

申请日：2021-02-02

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L25/16 ,  H01L25/18 ,  H10B63/00 ,  G11C5/06 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10N70/00

CPC classification number: H10B63/84 ,  G11C5/063 ,  H01L25/16 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B63/34 ,  H10N70/011 ,  H10N70/882

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a first control logic region comprising first control logic devices, and a first memory array region vertically overlying the first control logic region and comprising an array of vertically extending strings of memory cells. An additional microelectronic device structure comprising a semiconductive material is attached to an upper surface of the microelectronic device structure. A portion of the semiconductive material is removed. A second control logic region is formed over the first memory array region. The second control logic region comprises second control logic devices and a remaining portion of the semiconductive material. A second memory array region is formed over the second control logic region. The second memory array region comprises an array of resistance variable memory cells. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US11710724B2

公开(公告)日：2023-07-25

申请号：US17649022

申请日：2022-01-26

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Paolo Tessariol ,  Akira Goda

IPC: H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/768 ,  H01L23/481 ,  H01L23/4827 ,  H01L24/05 ,  H01L25/50

Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

公开(公告)号：US20230143455A1

公开(公告)日：2023-05-11

申请号：US18149318

申请日：2023-01-03

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H10B41/27 ,  H10B43/27 ,  G11C5/02 ,  H01L23/522 ,  H01L23/532 ,  G11C5/06

CPC classification number: H01L27/11556 ,  H01L27/11582 ,  G11C5/025 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  G11C5/06

Abstract: A microelectronic device comprises a memory array region, a control logic region underlying the memory array region, and an interconnect region vertically interposed between the memory array region and the control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures; vertically extending strings of memory cells within the stack structure; at least one source structure vertically overlying the stack structure and coupled to the vertically extending strings of memory cells; and digit line structures vertically underlying the stack structure and coupled to the vertically extending strings of memory cells. The control logic region comprises control logic devices for the vertically extending strings of memory cells. The interconnect region comprises structures coupling the digit line structures to the control logic devices. Methods of forming a microelectronic device, and memory devices and electronic systems are also described.