公开(公告)号：US11816871B2

公开(公告)日：2023-11-14

申请号：US17138817

申请日：2020-12-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Tung Chuen Kwong ,  David Porpino Sobreira Marques ,  King Chiu Tam ,  Shilpa Rajagopalan ,  Benjamin Koon Pan Chan ,  Vickie Youmin Wu

IPC: G06T9/00 ,  G06N3/02 ,  G06T3/40

CPC classification number: G06T9/002 ,  G06N3/02 ,  G06T3/4046

Abstract: Methods and devices are provided for processing image data on a sub-frame portion basis using layers of a convolutional neural network. The processing device comprises memory and a processor. The processor is configured to receive frames of image data comprising sub-frame portions, schedule a first sub-frame portion of a first frame to be processed by a first layer of the convolutional neural network when the first sub-frame portion is available for processing, process the first sub-frame portion by the first layer and continue the processing of the first sub-frame portion by the first layer when it is determined that there is sufficient image data available for the first layer to continue processing of the first sub-frame portion. Processing on a sub-frame portion basis continues for subsequent layers such that processing by a layer can begin as soon as sufficient data is available for the layer.

公开(公告)号：US20230359556A1

公开(公告)日：2023-11-09

申请号：US17735469

申请日：2022-05-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  Marko Scrbak

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: An electronic device includes a processor and a memory separate from the processor. The memory includes memory circuitry including a plurality of locations and processor in memory circuitry. In some implementations, some or all of the locations are used for storing cache blocks for a cache memory and the processor in memory circuitry performs operations for handling cache blocks in the memory circuitry. In some implementations, some or all of the locations are used for storing data for a memory and the processor in memory circuitry performs operations for handling data in the memory circuitry.

公开(公告)号：US11810891B2

公开(公告)日：2023-11-07

申请号：US17189324

申请日：2021-03-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Priyal Shah ,  Milind S. Bhagavat

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L2224/0384 ,  H01L2224/05082 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05557 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/0614 ,  H01L2224/06515 ,  H01L2224/08146 ,  H01L2224/8034 ,  H01L2224/8089 ,  H01L2224/80801 ,  H01L2224/80906

Abstract: Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.

公开(公告)号：US11809260B2

公开(公告)日：2023-11-07

申请号：US17029042

申请日：2020-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Martin McAfee ,  David L Wigton

IPC: G06F1/32 ,  G06F1/3296 ,  G06F1/28 ,  G06F1/3287 ,  H02M3/155

CPC classification number: G06F1/3296 ,  G06F1/28 ,  G06F1/3287 ,  H02M3/155

Abstract: A method of operating a multiphase power supply includes identifying a least efficient phase of a plurality of phases in the multiphase power supply based on a comparison of a pulse width for each phase in the plurality of phases, and decreasing an amount of power supplied to a load by the identified least efficient phase.

公开(公告)号：US20230351667A1

公开(公告)日：2023-11-02

申请号：US17957768

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： John Alexandre Tsakok

IPC: G06T15/00

CPC classification number: G06T15/005 ,  G06T2210/21 ,  G06T2210/52 ,  G06T2210/12

Abstract: A technique for building a bounding volume hierarchy is disclosed. The technique includes performing a nearest neighbor search for a set of clusters to generate a set of nearest neighbors; without performing a global barrier operation, performing a merge operation for the set of clusters, based on the set of nearest neighbors to generate merge results for the set of clusters; and without performing a global barrier operation, outputting clusters for a level of the bounding volume hierarchy, based on the merge results.

公开(公告)号：US20230350485A1

公开(公告)日：2023-11-02

申请号：US18346380

申请日：2023-07-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Vedula Venkata Srikant Bharadwaj ,  Shomit Das ,  Anthony T. Gutierrez ,  Vignesh Adhinarayanan

IPC: G06F1/3287 ,  G06F9/50 ,  G06F1/3296 ,  G06F1/324

CPC classification number: G06F1/3287 ,  G06F9/50 ,  G06F1/3296 ,  G06F1/324

Abstract: Systems, methods, devices, and computer-implemented instructions for processor power management implemented in a compiler. In some implementations, a characteristic of code is determined. An instruction based on the determined characteristic is inserted into the code. The code and inserted instruction are compiled to generate compiled code. The compiled code is output.

公开(公告)号：US20230350480A1

公开(公告)日：2023-11-02

申请号：US18213596

申请日：2023-06-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Indrani Paul ,  Sriram Sambamurthy ,  Larry David Hewitt ,  Kevin M. Lepak ,  Samuel D. Naffziger ,  Adam Neil Calder Clark ,  Aaron Joseph Grenat ,  Steven Frederick Liepe ,  Sandhya Shyamasundar ,  Wonje Choi ,  Dana Glenn Lewis ,  Leonardo de Paula Rosa Piga

IPC: G06F1/3225 ,  G06F1/3234

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F1/3203

Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

公开(公告)号：US11803484B2

公开(公告)日：2023-10-31

申请号：US17512943

申请日：2021-10-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul Moyer

IPC: G06F12/123 ,  G06F12/0862 ,  G06F12/0888 ,  G06F12/12

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F12/0888 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/502 ,  G06F2212/6028

Abstract: A processor applies a software hint policy to a portion of a cache based on access metrics for different test regions of the cache, wherein each test region applies a different software hint policy for data associated with cache entries in each region of the cache. One test region applies a software hint policy under which software hints are followed. The other test region applies a software hint policy under which software hints are ignored. One of the software hint policies is selected for application to a non-test region of the cache.

公开(公告)号：US11803437B1

公开(公告)日：2023-10-31

申请号：US17854988

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Aaron D Willey ,  Karthik Gopalakrishnan

IPC: G06F11/00 ,  G06F11/07 ,  G06F12/123

CPC classification number: G06F11/076 ,  G06F11/073 ,  G06F12/123 ,  G06F2212/1008

Abstract: A memory includes a link training circuit with a pseudo-random bit sequence (PRBS) generator and a burst error detection counter. The burst error detection counter including a comparator, a first input coupled to the data input, a second input coupled to the PRBS generator, and a counter operable to increase an error count value by one responsive to detecting any number of errors greater than zero in a sequence of symbols including a predetermined number of symbols.

公开(公告)号：US11797665B1

公开(公告)日：2023-10-24

申请号：US16454690

申请日：2019-06-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： David Kaplan ,  Marius Evers

IPC: G06F9/455 ,  G06F21/53 ,  G06F21/74 ,  G06F9/38

CPC classification number: G06F21/53 ,  G06F9/45558 ,  G06F21/74 ,  G06F9/3806 ,  G06F2009/45587 ,  G06F2221/033

Abstract: A processing system includes a branch prediction structure storing information used to predict the outcome of a branch instruction. The processing system also includes a register storing a first identifier of a first process in response to the processing system changing from a first mode that allows the first process to modify the branch prediction structure to a second mode in which the branch prediction structure is not modifiable. The processing system further includes a processor core that selectively flushes the branch prediction structure based on a comparison of a second identifier of a second process and the first identifier stored in the register. The comparison is performed in response to the second process causing a change from the second mode to the first mode.