公开(公告)号：US08564970B2

公开(公告)日：2013-10-22

申请号：US12723321

申请日：2010-03-12

Applicant: Hung-Kun Chen ,  Chi-Chin Lin

Inventor： Hung-Kun Chen ,  Chi-Chin Lin

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H01L27/1259 ,  G09G3/3208 ,  G09G2300/0426 ,  H05K1/0268 ,  H05K3/0052 ,  H05K2201/09245 ,  H05K2201/09263 ,  H05K2201/09272 ,  H05K2203/175

Abstract: This invention discloses a display device mother substrate, a display device substrate and a manufacture method of display device substrate thereof. The display device mother substrate includes a first substrate, a second substrate, a first active area circuit and a first transmission line, wherein a first cutting line is defined between the first substrate and the second substrate. The first active area circuit is disposed on the first substrate and is electrically connected to the first transmission line. The first transmission line includes a display line portion, an end line portion and a middle line portion, wherein the display line portion is electrically connected to the first active area circuit. The middle line portion is disposed on the second substrate, wherein two ends of the middle line portion are electrically connected to the display line portion and the end line portion respectively at the first cutting line. The display device mother substrate is cut along the first cutting line to be separated into the first substrate and the second substrate, wherein the middle line portion is also separated from the display line portion and the end line portion.

Abstract translation: 本发明公开了一种显示装置母板，显示装置用基板及其显示装置用基板的制造方法。 显示装置母板包括第一基板，第二基板，第一有源区电路和第一传输线，其中在第一基板和第二基板之间限定第一切割线。 第一有源区电路设置在第一基板上，并与第一传输线电连接。 第一传输线包括显示线部分，端部线部分和中间线部分，其中显示线部分电连接到第一有源区电路。 中间线部分设置在第二基板上，其中中间线部分的两端分别在第一切割线处电连接到显示线部分和端部线部分。 显示装置母基板沿着第一切割线切割以分离成第一基板和第二基板，其中中间线部分也与显示线部分和端部线部分分离。

公开(公告)号：US08442210B2

公开(公告)日：2013-05-14

申请号：US12755376

申请日：2010-04-06

Applicant: Jared L. Zerbe

Inventor： Jared L. Zerbe

IPC: H04M1/00

CPC classification number: H04B3/32 ,  H01R13/6467 ,  H05K1/0228 ,  H05K2201/09245 ,  H05K2201/10689

Abstract: A signaling system is disclosed. The system includes a transmitter comprising an encoder to encode a data signal such that the encoded data signal has a balanced number of logical 1s and 0s. The system also includes a receiver having a decoder to decode the encoded data signal, and a link. The link is coupled between the transmitter and the receiver to route the encoded data signal. The link comprises three or more conductive lines that are routed along a path in parallel between the encoder and the decoder, and wherein the link comprises segments, each segment comprising a routing change to reorder proximity of at least one pair of lines relative to any adjacent segment, with a sufficient number of segments such that each line has each of the other lines of the link as a nearest neighbor over at least a portion of the path.

Abstract translation: 公开了一种信令系统。 该系统包括发射机，包括编码器，用于对数据信号进行编码，使得编码数据信号具有平衡数量的逻辑1和0。 该系统还包括具有用于解码编码数据信号的解码器的接收器和链路。 该链路耦合在发射机和接收机之间以路由编码的数据信号。 该链路包括沿编码器和解码器之间的并行路径路由的三条或更多条导线，并且其中链路包括段，每个段包括路由改变，以重新排列至少一对线相对于任何相邻 段，具有足够数量的段，使得每条线在链路的至少一部分上具有链路的每条其他线路作为最近邻居。

公开(公告)号：US20120286902A1

公开(公告)日：2012-11-15

申请号：US13394473

申请日：2010-09-01

Applicant: Manfred Michalk

Inventor： Manfred Michalk

IPC: H01P7/08 ,  B32B37/06 ,  B32B38/18 ,  B32B37/14

CPC classification number: H05K1/162 ,  G06K19/07749 ,  G06K19/07779 ,  H01F41/074 ,  H01L24/85 ,  H01L2224/78 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01Q7/00 ,  H01Q9/27 ,  H05K3/103 ,  H05K3/30 ,  H05K2201/09245 ,  H05K2201/09672 ,  H05K2201/1028 ,  Y10T156/10 ,  Y10T156/17 ,  H01L2924/00 ,  H01L2224/45099

Abstract: The present invention relates to a circuit arrangement (1) having a prescribed electrical capacitance, comprising a substrate (S) having at least one metallic, electrically conductive conductor (L, Lb, Ls). According to the invention, at least one first conductor strip segment (LA1) is disposed on the substrate (S) and at least some regions of at least one second conductor strip segment (LA2, LA3, LA4) are disposed on the first conductor strip segment (LA1), wherein an electrically insulating layer (iS) is disposed between the conductor strip segments (LA1, LA2, LA3, LA4), forming a dielectric. The invention further relates to a method and a device (2) for producing a circuit arrangement (1) having a prescribed electrical capacitance.

Abstract translation: 本发明涉及具有规定电容的电路装置（1），其包括具有至少一个金属导电导体（L，Lb，Ls）的基板（S）。 根据本发明，至少一个第一导体条段（LA1）设置在基板（S）上，并且至少一个第二导体条段（LA2，LA3，LA4）的至少一些区域设置在第一导体条 （LA1），其中电绝缘层（iS）设置在导体条段（LA1，LA2，LA3，LA4）之间，形成电介质。 本发明还涉及一种用于制造具有规定电容的电路装置（1）的方法和装置（2）。

公开(公告)号：US08169275B2

公开(公告)日：2012-05-01

申请号：US12894147

申请日：2010-09-30

Applicant: Wen-Tsai Tsai ,  Wen-Chen Lan

Inventor： Wen-Tsai Tsai ,  Wen-Chen Lan

IPC: H03H7/38 ,  H01P5/02

CPC classification number: H01P5/028 ,  H05K1/0237 ,  H05K2201/09245

Abstract: A circuit board with jumper structure is disclosed. The circuit board includes a substrate, a ground layer, a first signal transmission line, and a second signal transmission line. The ground layer is formed on a second plane of the substrate. The first signal transmission line is formed on a first plane of the substrate, and coupled to a first signal end and a second signal end. A first signal transmitted on the first signal transmission line in a combination method of a microstrip line to co-planar waveguide transition and a co-planar waveguide to microstrip line transition. The second signal transmission line is formed on the second plane of the substrate, and coupled to a third signal end and a fourth signal end. A second signal is transmitted on the second signal transmission line in the co-planar waveguide transmission.

Abstract translation: 公开了一种具有跳线结构的电路板。 电路板包括衬底，接地层，第一信号传输线和第二信号传输线。 接地层形成在基板的第二平面上。 第一信号传输线形成在衬底的第一平面上，并耦合到第一信号端和第二信号端。 在第一信号传输线上以微带线到共面波导过渡的组合方法和共平面波导到微带线转换的第一信号。 第二信号传输线形成在衬底的第二平面上，并耦合到第三信号端和第四信号端。 第二信号在共面波导传输中的第二信号传输线上传输。

公开(公告)号：US08071890B2

公开(公告)日：2011-12-06

申请号：US12181330

申请日：2008-07-29

Applicant: Chien-Min Hsu ,  Shih-Hsien Wu ,  Shinn-Juh Lai ,  Min-Lin Lee

Inventor： Chien-Min Hsu ,  Shih-Hsien Wu ,  Shinn-Juh Lai ,  Min-Lin Lee

IPC: H05K1/16

CPC classification number: H05K1/112 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K1/0228 ,  H05K1/0231 ,  H05K1/0263 ,  H05K1/162 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09245 ,  H05K2201/09627 ,  H05K2201/09709 ,  H05K2201/10734 ,  H01L2224/05599

Abstract: An electrically conductive structure includes a first conductive structure and a second conductive structure. Each has a conducting section at one end and a coupling section at the other end. The first and second conducting sections are electrically connected to a power and ground contact of an electronic device, respectively. The first and second coupling sections are respectively connected with power and ground layer of a circuit board. The first coupling sections are connected with the first conducting section through first extending sections and the second coupling sections are connected with the second conducting section through second extending sections. At least two coupling sections of the conductive structures are arranged in pairs. The first conductive structure and the second conductive structure are arranged in a staggered array to form two wiring loops having opposite current directions, thereby generating a magnetic flux cancellation effect.

Abstract translation: 导电结构包括第一导电结构和第二导电结构。 每个在一端具有导电部分，另一端具有耦合部分。 第一和第二导电部分分别电连接到电子设备的电源和接地触点。 第一和第二耦合部分分别与电路板的电源层和接地层连接。 第一耦合部分通过第一延伸部分与第一导电部分连接，第二耦合部分通过第二延伸部分与第二导电部分连接。 导电结构的至少两个耦合部分成对布置。 第一导电结构和第二导电结构以交错阵列布置以形成具有相反电流方向的两个布线环，从而产生磁通消除效果。

公开(公告)号：US08011972B2

公开(公告)日：2011-09-06

申请号：US11674359

申请日：2007-02-13

Applicant: Jack E. Caveney ,  Masud Bolouri-Saransar

Inventor： Jack E. Caveney ,  Masud Bolouri-Saransar

IPC: H01R24/00

CPC classification number: H01R13/6466 ,  H01R13/7195 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/162 ,  H05K1/189 ,  H05K2201/09245 ,  H05K2201/09263 ,  H05K2201/10189 ,  Y10S439/941

Abstract: A jack with a flexible printed circuit board (FPC) is provided. The FPC is connected to the plug interface contacts and has a compensation circuit to compensate for near-end crosstalk (NEXT) and far-end crosstalk (FEXT). Capacitive and inductive compensation in the compensation circuit are of opposite polarity and are substantially equal in magnitude. The compensation circuit has a FEXT compensation zone containing compensation for the FEXT. Inductive and capacitive compensation in the FEXT compensation zone are distributed.

Abstract translation: 提供具有柔性印刷电路板（FPC）的插座。 FPC连接到插头接口触点，并具有补偿电路以补偿近端串扰（NEXT）和远端串扰（FEXT）。 补偿电路中的电容和电感补偿极性相反，且幅度基本相等。 补偿电路具有FEXT补偿区域，其中包含FEXT的补偿。 分布式FEXT补偿区域的感性和电容补偿。

公开(公告)号：US20100200276A1

公开(公告)日：2010-08-12

申请号：US12537430

申请日：2009-08-07

Applicant: Sampath Komarapalayam Velayudham Karikalan

Inventor： Sampath Komarapalayam Velayudham Karikalan

IPC: H05K1/00 ,  H05K3/10

CPC classification number: H05K1/0245 ,  H05K2201/09245 ,  H05K2201/097 ,  Y10T29/49155

Abstract: A twisted differential conductor pair is formed on a circuit board that includes first-third conductors. The second conductor includes first-third portions. The second portion of the second conductor extends between an end of the first conductor and an end of the third conductor, and couples an end of the first portion of the second conductor to an end of the third portion of the second conductor. A solder mask layer is formed over the first, second, and third conductors on the circuit board. An end of the first conductor and the end of the third conductor are exposed through the solder mask layer. The exposed end of the first conductor is coupled to the exposed end of the third conductor over the solder mask layer with a bridge. This configuration may be repeated to create multiple twists along the twisted differential conductor pair.

Abstract translation: 在包括第一至第三导体的电路板上形成扭曲的差分导体对。 第二导体包括第一第三部分。 第二导体的第二部分在第一导体的端部和第三导体的端部之间延伸，并且将第二导体的第一部分的端部耦合到第二导体的第三部分的端部。 在电路板上的第一，第二和第三导体上形成焊接掩模层。 第一导体的一端和第三导体的端部通过焊接掩模层露出。 第一导体的暴露端通过桥接在焊料掩模层上与第三导体的暴露端耦合。 可以重复该配置以沿着扭曲的差分导体对产生多个扭曲。

公开(公告)号：US20100184307A1

公开(公告)日：2010-07-22

申请号：US12613501

申请日：2009-11-05

Applicant: Tatsuya Arai ,  Ching-Chao Huang ,  Clement Kam Lam Luk ,  Jeremy Buan ,  Tsutomu Matsuo ,  Toshiyuki Takada ,  Masakazu Nagata

Inventor： Tatsuya Arai ,  Ching-Chao Huang ,  Clement Kam Lam Luk ,  Jeremy Buan ,  Tsutomu Matsuo ,  Toshiyuki Takada ,  Masakazu Nagata

IPC: H01R12/00

CPC classification number: H04M1/76 ,  H05K1/0245 ,  H05K2201/09245 ,  H05K2201/10689

Abstract: The present invention involves connectors for reducing Far-End Crosstalk (FEXT) through the use of novel polarity swapping to negate the cumulative effect of FEXT. Skew adjustment is used to improve the FEXT cancellation from polarity swapping. The polarity reversal location or locations among FEXT sources are optimized to achieve maximum FEXT cancellation. The novelty polarity swapping technique can be applied to a wide variety of connectors, such as mezzanine connectors, backplane connectors, and any other connectors that can benefit from FEXT reduction.

Abstract translation: 本发明涉及通过使用新的极性交换来减少FEXT的累积效应来减少远端串扰（FEXT）的连接器。 倾斜调整用于改善极性交换中的FEXT消除。 FEXT源中的极性反转位置或位置被优化，以实现最大的FEXT取消。 新颖的极性交换技术可以应用于各种连接器，例如夹层连接器，背板连接器以及可以从FEXT减少中受益的任何其他连接器。

公开(公告)号：US20090057000A1

公开(公告)日：2009-03-05

申请号：US12230361

申请日：2008-08-28

Applicant: Robert Kraus ,  Simon Schwalenberg ,  Steffen Strauss ,  Michael Weis

Inventor： Robert Kraus ,  Simon Schwalenberg ,  Steffen Strauss ,  Michael Weis

IPC: H05K1/11

CPC classification number: H05K3/222 ,  F21K9/00 ,  H05K1/181 ,  H05K2201/09245 ,  H05K2201/09418 ,  H05K2201/10106 ,  H05K2203/049

Abstract: Connecting element for mounting on a printed circuit board, which connecting element has at least two connecting lines which cross one another and are not electrically connected between respectively associated contacts.

Abstract translation: 用于安装在印刷电路板上的连接元件，该连接元件具有彼此交叉且不电连接在分别相关联的触点之间的至少两条连接线。

公开(公告)号：US07459987B2

公开(公告)日：2008-12-02

申请号：US10575795

申请日：2004-09-17

Applicant: Andreas Przadka

Inventor： Andreas Przadka

IPC: H03H7/38

CPC classification number: H01P5/02 ,  H05K1/0239 ,  H05K1/0306 ,  H05K1/162 ,  H05K2201/09245 ,  H05K2201/09263

Abstract: A network for electrical matching of an electrical component is disclosed. The network includes n first conductor plane and a second conductor plane separated by a ceramic intermediate layer. The network also includes a transformation line formed in or on a substrate and having a predetermined electrical length. The transformation line includes a first part having a bent-over configuration and a second part having a bent-over configuration. The first part is disposed in a first plane and the second part is disposed in a second plane. The second part is electrically connected to the first part by an interlayer contact to the ceramic intermediate layer.

Abstract translation: 公开了一种用于电气部件的电气匹配的网络。 网络包括由陶瓷中间层隔开的第一导体平面和第二导体平面。 网络还包括形成在基底中或基底上并具有预定电长度的变换线。 变形线包括具有弯曲构造的第一部分和具有弯曲构造的第二部分。 第一部分设置在第一平面中，第二部分设置在第二平面中。 第二部分通过陶瓷中间层中的层间接触电连接到第一部分。