公开(公告)号：US20230297533A1

公开(公告)日：2023-09-21

申请号：US18322183

申请日：2023-05-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JASON R. TALBERT

IPC: G06F13/40 ,  G06F13/20

CPC classification number: G06F13/4027 ,  G06F13/20 ,  G06F9/4405

Abstract: Signal bridging using an unpopulated processor interconnect, including: communicatively coupling an apparatus to a plurality of first signal paths between a bootstrap processor (BSP) and a processor interconnect of a circuit board; communicatively coupling the apparatus to a plurality of second signal paths between the processor interconnect and a peripheral interface of the circuit board; and communicatively coupling the BSP to the peripheral interface via one or more third signal paths in the apparatus.

公开(公告)号：US20230297381A1

公开(公告)日：2023-09-21

申请号：US17699855

申请日：2022-03-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Chetana N. Keltcher ,  Alok Garg ,  Paul S Keltcher

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30043

Abstract: Load dependent branch prediction is described. In accordance with described techniques, a load dependent branch instruction is detected by identifying that a destination location of a load instruction is used in an operation for determining whether a conditional branch is taken or not taken. The load instruction is included in a sequence of load instructions having addresses separated by a step size. An instruction is injected in an instruction stream of a processor for fetching data of a future load instruction using an address of the load instruction offset by a distance based on the step size. An additional instruction is injected in the instruction stream of the processor for precomputing an outcome of a load dependent branch using an address computed based on an address of the operation and the data of the future load instruction.

公开(公告)号：US11762777B2

公开(公告)日：2023-09-19

申请号：US17219782

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  Marko Scrbak ,  Matthew Raymond Poremba

IPC: G06F12/0891 ,  G06F12/0853 ,  G06F3/06 ,  G06F12/0862

CPC classification number: G06F12/0891 ,  G06F3/0614 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0853 ,  G06F12/0862

Abstract: Devices and methods for cache prefetching are provided. A device is provided which comprises memory and a processor. The memory comprises a DRAM cache, a cache dedicated to the processor and one or more intermediate caches between the dedicated cache and the DRAM cache. The processor is configured to issue prefetch requests to prefetch data, issue data access requests to fetch the data and when one or more previously issued prefetch requests are determined to be inaccurate, issue a prefetch request to prefetch a tag, corresponding to the memory address of requested data in the DRAM cache. A tag look-up is performed at the DRAM cache without performing tag look-ups at the dedicated cache or the intermediate caches. The tag is prefetched from the DRAM cache without prefetching the requested data.

公开(公告)号：US20230289070A1

公开(公告)日：2023-09-14

申请号：US18320819

申请日：2023-05-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael W. LeBeane ,  Khaled Hamidouche ,  Hari S. Thangirala ,  Brandon Keith Potter

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0802

CPC classification number: G06F3/0619 ,  G06F12/0223 ,  G06F3/0656 ,  G06F3/067 ,  G06F12/0802 ,  G06F2212/152

Abstract: A framework disclosed herein extends a relaxed, scoped memory model to a system that includes nodes across a commodity network and maintains coherency across the system. A new scope, cluster scope, is defined, that allows for memory accesses at scopes less than cluster scope to operate on locally cached versions of remote data from across the commodity network without having to issue expensive network operations. Cluster scope operations generate network commands that are used to synchronize memory across the commodity network.

公开(公告)号：US11755477B2

公开(公告)日：2023-09-12

申请号：US17563675

申请日：2021-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Chintan S. Patel ,  Girish Balaiah Aswathaiya

IPC: G06F12/00 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/604

Abstract: A cache includes an upstream port, a downstream port, a cache memory, and a control circuit. The control circuit temporarily stores memory access requests received from the upstream port, and checks for dependencies for a new memory access request with older memory access requests temporarily stored therein. If one of the older memory access requests creates a false dependency with the new memory access request, the control circuit drops an allocation of a cache line to the cache memory for the older memory access request while continuing to process the new memory access request.

公开(公告)号：US11755336B2

公开(公告)日：2023-09-12

申请号：US17489059

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Todd Martin ,  Tad Robert Litwiller ,  Nishank Pathak ,  Randy Wayne Ramsey

IPC: G06T1/60 ,  G06F9/4401 ,  G06F9/30 ,  G06F9/54

CPC classification number: G06F9/4411 ,  G06F9/3009 ,  G06F9/544

Abstract: Systems, apparatuses, and methods for performing geometry work in parallel on multiple chiplets are disclosed. A system includes a chiplet processor with multiple chiplets for performing graphics work in parallel. Instead of having a central distributor to distribute work to the individual chiplets, each chiplet determines on its own the work to be performed. For example, during a draw call, each chiplet calculates which portions to fetch and process of one or more index buffer(s) corresponding to one or more graphics object(s) of the draw call. Once the portions are calculated, each chiplet fetches the corresponding indices and processes the indices. The chiplets perform these tasks in parallel and independently of each other. When the index buffer(s) are processed, one or more subsequent step(s) in the graphics rendering process are performed in parallel by the chiplets.

公开(公告)号：US20230280819A1

公开(公告)日：2023-09-07

申请号：US18316865

申请日：2023-05-12

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Alexander J. Branover ,  Christopher T. Weaver ,  Benjamin Tsien ,  Indrani Paul ,  Mihir Shaileshbhai Doctor ,  Thomas J. Gibney ,  John P. Petry ,  Dennis Au ,  Oswin Hall

IPC: G06F1/3234 ,  G06F1/3209

CPC classification number: G06F1/3265 ,  G06F1/3209 ,  G06F1/3275

Abstract: A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.

公开(公告)号：US11742301B2

公开(公告)日：2023-08-29

申请号：US16544021

申请日：2019-08-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rahul Agarwal ,  Milind S. Bhagavat ,  Priyal Shah ,  Chia-Hao Cheng ,  Brett P. Wilkerson ,  Lei Fu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a fan-out redistribution layer (RDL) structure that has plural stacked polymer layers, plural metallization layers, plural conductive vias interconnecting adjacent metallization layers of the metallization layers, and plural rivets configured to resist delamination of one or more of the polymer layers. Each of the plural rivets includes a first head, a second head and a shank connected between the first head and the second head. The first head is part of one of the metallization layers. The shank includes at least one of the conductive vias and at least one part of another of the metallization layers.

公开(公告)号：US11742038B2

公开(公告)日：2023-08-29

申请号：US15857887

申请日：2017-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Steven Raasch ,  Greg Sadowski ,  David A. Roberts

IPC: G11C16/34 ,  G06F12/02 ,  G06F3/06 ,  G06F9/50 ,  G11C29/00 ,  G11C11/4076 ,  G11C7/04

CPC classification number: G11C16/3495 ,  G06F3/064 ,  G06F3/0616 ,  G06F3/0679 ,  G06F9/50 ,  G06F12/0223 ,  G06F12/0246 ,  G11C7/04 ,  G11C11/4076 ,  G11C16/349 ,  G11C16/3418 ,  G11C29/70 ,  G06F2212/1036 ,  G06F2212/7211

Abstract: Exemplary embodiments provide wear spreading among die regions (i.e., one or more circuits) in an integrated circuit or among dies by using operating condition data in addition to or instead of environmental data such as temperature data, from each of a plurality of die regions. Control logic produces a cumulative amount of time each of the plurality of die regions has spent at an operating condition based on operating condition data wherein the operating condition data is based on at least one of the following operating characteristics: frequency of operation of the plurality of die regions, an operating voltage of the plurality of die regions, an activity level of the plurality of die regions, a timing margin of the plurality of die regions, and a number of detected faults of the plurality of die regions. The method and apparatus spreads wear among the plurality of same type of die regions by controlling task execution among the plurality of die regions using the die wear-out data.

公开(公告)号：US11741658B2

公开(公告)日：2023-08-29

申请号：US17564186

申请日：2021-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Konstantin Igorevich Shkurko

IPC: G06T15/06 ,  G06T15/30 ,  G06T15/08 ,  G06T17/10 ,  G06T15/20

CPC classification number: G06T15/06 ,  G06T15/08 ,  G06T15/20 ,  G06T15/30 ,  G06T17/10 ,  G06T2210/21

Abstract: A frustum bounds a subset of rays projected into a virtual scene to be rendered. The frustum is transformed from a Cartesian coordinate space to a spherical coordinate space using a transform matrix that places a central ray of the frustum as the Z-axis. A projection hemisphere centered around the central ray is defined. The extents of the intersection of the transformed frustum and the surface of the projection hemisphere are bound by a frustum circle. A geometric object in the scene or a bounding volume is bound by a bounding sphere, which is transformed into the spherical coordinate system using the transform matrix, and then projected onto the surface of the projection sphere to define a bounding circle. The frustum is identified as intersecting the geometric object or bounding volume responsive to angular overlap and distance overlap between the frustum circle and the bounding circle.