公开(公告)号：US09595662B2

公开(公告)日：2017-03-14

申请号：US15213384

申请日：2016-07-18

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Yu Lu ,  Seung Hyuk Kang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetoresistive random-access memory (MRAM) integration compatible with shrinking device technologies includes a magnetic tunnel junction (MTJ) formed in a common interlayer metal dielectric (IMD) layer with one or more logic elements. The MTJ is connected to a bottom metal line in a bottom IMD layer and a top via connected to a top IMD layer. The MTJ substantially extends between one or more bottom cap layers configured to separate the common IMD layer and the bottom IMD layer and one or more top cap layers configured to separate the common IMD layer and the top IMD layer. The MTJ can include a top electrode to connect to the top via or be directly connected to the top via through a hard mask for smaller device technologies. The logic elements include vias, metal lines, and semiconductor devices.

Abstract translation: 与收缩装置技术兼容的磁阻随机存取存储器（MRAM）集成包括形成在具有一个或多个逻辑元件的公共夹层金属电介质（IMD）层中的磁性隧道结（MTJ）。 MTJ连接到底部IMD层中的底部金属线和连接到顶部IMD层的顶部通孔。 MTJ基本上在配置成分离公共IMD层和底部IMD层的一个或多个底盖层之间延伸，以及被配置为分离公共IMD层和顶部IMD层的一个或多个顶盖层。 MTJ可以包括顶部电极，以连接到顶部通孔，或者通过用于较小器件技术的硬掩模直接连接到顶部通孔。 逻辑元件包括通孔，金属线和半导体器件。

公开(公告)号：US09543036B2

公开(公告)日：2017-01-10

申请号：US14820101

申请日：2015-08-06

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Xiaochun Zhu

IPC: G11C11/34 ,  G11C11/40 ,  G11C17/12 ,  G11C5/02 ,  G11C17/08 ,  G11C7/00 ,  G11C17/16 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78 ,  G11C7/12 ,  G11C11/404

CPC classification number: G11C17/08 ,  G11C7/00 ,  G11C7/12 ,  G11C11/40 ,  G11C11/404 ,  G11C17/16 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/10802 ,  H01L29/7841

Abstract: A method includes applying a programming voltage to a drain of an access transistor, where a source of the access transistor is coupled to a drain region of a one-time programmable (OTP) device. The method also includes applying a first voltage to a gate of the OTP device and a second voltage to a terminal of the OTP device to bias a channel region of the OTP device, where the first voltage and the second voltage are substantially equal.

Abstract translation: 一种方法包括将编程电压施加到存取晶体管的漏极，其中存取晶体管的源极耦合到一次可编程（OTP）器件的漏极区。 该方法还包括将第一电压施加到OTP器件的栅极，并将第二电压施加到OTP器件的端子以偏置OTP器件的沟道区域，其中第一电压和第二电压基本相等。

公开(公告)号：US09514795B1

公开(公告)日：2016-12-06

申请号：US14835871

申请日：2015-08-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Yu Lu ,  Xiaochun Zhu

IPC: G11C11/00 ,  G11C11/16

Abstract: Reverse complement MTJ bit cells employing shared source lines are disclosed. In one aspect, a 2T2MTJ reverse complement bit cell employing shared source line is provided. Bit cell includes first MTJ and second MTJ. Value of first MTJ is complement of value of second MTJ. First bit line is coupled to top layer of first MTJ, and first electrode of first access transistor is coupled to bottom layer of first MTJ. Second bit line is coupled to bottom layer of second MTJ, and first electrode of second access transistor is coupled to top layer of second MTJ. Word line is coupled to second electrode of first access transistor and second access transistor. Shared source line is coupled to third electrode of first access transistor and second access transistor. Employing shared source line allows the bit cell to be designed with reduced parasitic resistance.

公开(公告)号：US09461055B2

公开(公告)日：2016-10-04

申请号：US14280213

申请日：2014-05-16

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Zhongze Wang ,  Daniel Wayne Perry

IPC: H01L27/112 ,  G11C11/40 ,  G11C7/00 ,  G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L27/112 ,  G11C7/00 ,  G11C11/40 ,  G11C16/0475 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7923

Abstract: An advanced metal-nitride-oxide-silicon (MNOS) multiple time programmable (MTP) memory is provided. In an example, an apparatus includes a two field effect transistor (2T field FET) metal-nitride-oxide-silicon (MNOS) MTP memory. The 2T field FET MNOS MTP memory can include an interlayer dielectric (ILD) oxide region that is formed on a well and separates respective gates of first and second transistors from the well. A control gate is located between the respective gates of the first and second transistors, and a silicon-nitride-oxide (SiN) region is located between a metal portion of the control gate and a portion of the ILD oxide region.

Abstract translation: 提供先进的金属氮化物 - 氧化物 - 硅（MNOS）多时间可编程（MTP）存储器。 在一个示例中，装置包括两个场效应晶体管（2T场FET）金属氮化物 - 氧化物 - 硅（MNOS）MTP存储器。 2T场FET MNOS MTP存储器可以包括形成在阱上的层间电介质（ILD）氧化物区域，并将第一和第二晶体管的相应栅极与阱分离。 控制栅极位于第一和第二晶体管的各个栅极之间，并且氮化硅 - 氧化物（SiN）区域位于控制栅极的金属部分和ILD氧化物区域的一部分之间。

公开(公告)号：US09449709B1

公开(公告)日：2016-09-20

申请号：US14863417

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiaonan Chen ,  Niladri Narayan Mojumder ,  Zhongze Wang ,  Weidan Li

IPC: G11C11/00 ,  G11C17/18 ,  G11C11/419 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C7/02 ,  G11C11/4125 ,  G11C11/419 ,  G11C17/146

Abstract: A volatile and one-time program (OTP) compatible asymmetric memory cell may include a first pull-up transistor having a first threshold voltage. The asymmetric memory cell may also include a second pull-up transistor having a second threshold voltage that differs from the first threshold voltage. The asymmetric memory cell may further include a switch coupled to a well of the first pull-up transistor and the second pull-up transistor to alternate between a program voltage (Vpg) and a power supply voltage. The asymmetric memory cell may also include a peripheral switching circuit to control programming of the asymmetric memory cell.

Abstract translation: 易失性和一次性程序（OTP）兼容非对称存储单元可以包括具有第一阈值电压的第一上拉晶体管。 非对称存储单元还可以包括具有不同于第一阈值电压的第二阈值电压的第二上拉晶体管。 非对称存储单元还可以包括耦合到第一上拉晶体管和第二上拉晶体管的阱的开关，以在编程电压（Vpg）和电源电压之间交替。 非对称存储单元还可以包括用于控制非对称存储单元的编程的外围开关电路。

公开(公告)号：US20160267957A1

公开(公告)日：2016-09-15

申请号：US14645213

申请日：2015-03-11

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Xia Li

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/5607

Abstract: A device includes a first magnetic tunnel junction (MTJ) element having a first read margin and a second MTJ element having a second read margin. The first read margin is greater than twice the second read margin. The device also includes an access transistor coupled between the first MTJ element and the second MTJ element. A gate of the access transistor is coupled to a word line. The first MTJ element, the second MTJ element, and the access transistor form a multi-bit spin torque transfer magnetoresistive random access memory (STT-MRAM) memory cell.

Abstract translation: 一种装置包括具有第一读取余量的第一磁性隧道结（MTJ）元件和具有第二读取余量的第二MTJ元件。 第一个读取边距大于第二个读取边距的两倍。 该器件还包括耦合在第一MTJ元件和第二MTJ元件之间的存取晶体管。 存取晶体管的栅极耦合到字线。 第一MTJ元件，第二MTJ元件和存取晶体管形成多位自旋转矩传递磁阻随机存取存储器（STT-MRAM）存储单元。

公开(公告)号：US09437272B1

公开(公告)日：2016-09-06

申请号：US14645213

申请日：2015-03-11

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Xia Li

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/5607

Abstract: A device includes a first magnetic tunnel junction (MTJ) element having a first read margin and a second MTJ element having a second read margin. The first read margin is greater than twice the second read margin. The device also includes an access transistor coupled between the first MTJ element and the second MTJ element. A gate of the access transistor is coupled to a word line. The first MTJ element, the second MTJ element, and the access transistor form a multi-bit spin torque transfer magnetoresistive random access memory (STT-MRAM) memory cell.

Abstract translation: 一种装置包括具有第一读取余量的第一磁性隧道结（MTJ）元件和具有第二读取余量的第二MTJ元件。 第一个读取边距大于第二个读取边距的两倍。 该器件还包括耦合在第一MTJ元件和第二MTJ元件之间的存取晶体管。 存取晶体管的栅极耦合到字线。 第一MTJ元件，第二MTJ元件和存取晶体管形成多位自旋转矩传递磁阻随机存取存储器（STT-MRAM）存储单元。

公开(公告)号：US09412818B2

公开(公告)日：2016-08-09

申请号：US14100489

申请日：2013-12-09

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  PR Chidambaram ,  Choh Fei Yeap

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/20 ,  H01L29/22 ,  H01L21/8234

CPC classification number: H01L29/0684 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66795 ,  H01L29/785

Abstract: An apparatus comprises a first fin field effect transistor (FinFET) device extending from a surface of a first etch stop layer. The apparatus also comprises a second FinFET device extending from a surface of a second etch stop layer. A first compound layer is interposed between the first etch stop layer and the second etch stop layer.

Abstract translation: 一种装置包括从第一蚀刻停止层的表面延伸的第一鳍状场效应晶体管（FinFET）器件。 该装置还包括从第二蚀刻停止层的表面延伸的第二FinFET器件。 第一化合物层介于第一蚀刻停止层和第二蚀刻停止层之间。

公开(公告)号：US09373412B2

公开(公告)日：2016-06-21

申请号：US14570577

申请日：2014-12-15

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang

IPC: G11C5/14 ,  G11C16/30 ,  G11C16/04 ,  G11C5/06 ,  G11C17/18 ,  G11C7/12 ,  G06F17/50 ,  G11C11/40 ,  G11C17/16 ,  G11C11/404

CPC classification number: G11C17/18 ,  G06F17/5045 ,  G11C5/06 ,  G11C5/146 ,  G11C7/12 ,  G11C11/40 ,  G11C11/404 ,  G11C11/5692 ,  G11C16/04 ,  G11C17/16 ,  G11C2211/4016

Abstract: An apparatus includes a semiconductor transistor structure. The semiconductor transistor structure includes dielectric material, a channel region, a gate, a source overlap region, and a drain overlap region. The source overlap region is biasable to cause a first voltage difference between the source overlap region and the gate to exceed a breakdown voltage of the dielectric material. The drain overlap region is biasable to cause a second voltage difference between the drain overlap region and the gate to exceed the breakdown voltage. The apparatus includes a well line coupled to a body of the semiconductor transistor. The apparatus includes circuitry configured to apply a voltage to the well line to prevent a breakdown condition between the channel region and the gate.

Abstract translation: 一种装置包括半导体晶体管结构。 半导体晶体管结构包括电介质材料，沟道区，栅极，源极重叠区域和漏极重叠区域。 源重叠区域是可偏置的，以使源重叠区域和栅极之间的第一电压差超过电介质材料的击穿电压。 漏极重叠区域是可偏置的，以使漏极重叠区域和栅极之间的第二电压差超过击穿电压。 该装置包括耦合到半导体晶体管的本体的阱线。 该装置包括被配置为向阱管线施加电压以防止沟道区域和栅极之间的击穿状态的电路。

公开(公告)号：US20160064391A1

公开(公告)日：2016-03-03

申请号：US14469341

申请日：2014-08-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Woo Tag Kang ,  Changhan Hobie Yun ,  Wei-Chuan Chen

IPC: H01L27/115 ,  G11C11/409 ,  G11C11/22 ,  H01L27/108

CPC classification number: H01L27/11507 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/401 ,  G11C11/409 ,  H01G7/06 ,  H01L27/10805 ,  H01L27/10808 ,  H01L27/10897 ,  H01L27/11512 ,  H01L27/11514 ,  H01L28/91

Abstract: A memory cell includes a capacitor that includes a first metal layer and a second metal layer. The capacitor includes a ferroelectric layer disposed between the first metal layer and the second metal layer. The ferroelectric layer is a single layer of a bi-stable asymmetric crystalline material.

Abstract translation: 存储单元包括包括第一金属层和第二金属层的电容器。 电容器包括设置在第一金属层和第二金属层之间的铁电层。 铁电层是单层双稳态不对称结晶材料。