公开(公告)号：US20120168882A1

公开(公告)日：2012-07-05

申请号：US13285911

申请日：2011-10-31

Applicant: Suman Cherian ,  Olivier Le Neel

Inventor： Suman Cherian ,  Olivier Le Neel

IPC: H01L27/14 ,  H01L21/02

CPC classification number: G01N33/48785 ,  Y02B10/70 ,  Y10T436/143333 ,  Y10T436/144444 ,  Y10T436/172307 ,  Y10T436/184 ,  Y10T436/19 ,  Y10T436/204998 ,  Y10T436/205831

Abstract: A integrated circuit die includes a chemical sensor, a thermal sensor, and a humidity sensor formed therein. The chemical sensor, thermal sensor, and humidity sensor include electrodes formed in a passivation layer of the integrated circuit die. The integrated circuit die further includes transistors formed in a monocrystalline semiconductor layer.

Abstract translation: 集成电路管芯包括形成在其中的化学传感器，热传感器和湿度传感器。 化学传感器，热传感器和湿度传感器包括形成在集成电路管芯的钝化层中的电极。 集成电路管芯还包括形成在单晶半导体层中的晶体管。

公开(公告)号：US20120168754A1

公开(公告)日：2012-07-05

申请号：US12981375

申请日：2010-12-29

Applicant: Olivier Le Neel ,  Ravi Shankar ,  Calvin Leung

Inventor： Olivier Le Neel ,  Ravi Shankar ,  Calvin Leung

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L49/00 ,  H01L29/66742 ,  H01L29/786 ,  H01L29/78684 ,  Y10S257/902

Abstract: A transistor is formed having a thin film metal channel region. The transistor may be formed at the surface of a semiconductor substrate, an insulating substrate, or between dielectric layers above a substrate. A plurality of transistors each having a thin film metal channel region may be formed. Multiple arrays of such transistors can be vertically stacked in a same device.

Abstract translation: 形成具有薄膜金属沟道区的晶体管。 晶体管可以形成在半导体衬底的表面，绝缘衬底或衬底之上的电介质层之间。 可以形成各自具有薄膜金属沟道区的多个晶体管。 这种晶体管的多个阵列可以垂直地堆叠在相同的器件中。

公开(公告)号：US08148829B2

公开(公告)日：2012-04-03

申请号：US12650411

申请日：2009-12-30

Applicant: Guojun Hu

Inventor： Guojun Hu

IPC: H01L23/29

CPC classification number: H01L23/3142 ,  H01L23/295 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package comprises a molding compound covering a semiconductor die. A healing substance is on the surface of the semiconductor die at an interface of the molding compound and the semiconductor die. The healing compound comprises a catalyst and a plurality of microcapsules containing a sealing compound. If the molding compound becomes delaminated from the semiconductor die the microcapsules rupture and spill the sealing compound. When the sealing compound is spilled and contacts the catalyst the sealing compound and catalyst polymerize and fasten the molding compound to the semiconductor die.

Abstract translation: 集成电路封装包括覆盖半导体管芯的模塑料。 愈合物质在模塑料和半导体管芯的界面处在半导体管芯的表面上。 愈合组合物包含催化剂和含有密封化合物的多个微胶囊。 如果模塑料从半导体芯片脱层，则微胶囊破裂并溢出密封剂。 当密封化合物溢出并与催化剂接触时，密封化合物和催化剂聚合并将模塑料紧固到半导体管芯上。

公开(公告)号：US20250079189A1

公开(公告)日：2025-03-06

申请号：US18951814

申请日：2024-11-19

Applicant: STMicroelectronics Pte Ltd

Inventor： Jing-En LUAN

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01S5/02218 ,  H01S5/02315 ,  H01S5/02345

Abstract: A molded carrier is formed by a unitary body made of a laser direct structuring (LDS) material and includes a blind opening with a bottom surface. The unitary body includes: a floor body portion defining a back side and the bottom surface of the blind opening and an outer peripheral wall body portion defining a sidewall surface of the blind opening. LDS activation followed by electro-plating is used to produce: a die attach pad and bonding pad at the bottom surface; land grid array (LGA) pads at the back side; and vias extending through the floor body portion to make electrical connections between the die attach pad and one LGA pad and between the bonding pad and another LGA pad. An integrated circuit chip is mounted to the die attach pad and wire bonded to the bonding pad. A wafer-scale manufacturing process is used to form the molded carrier.

公开(公告)号：US12002898B2

公开(公告)日：2024-06-04

申请号：US17344520

申请日：2021-06-10

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En Luan

IPC: H01L31/12 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/18

CPC classification number: H01L31/12 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/186

Abstract: The present disclosure is directed to a sensor die with an embedded light sensor and an embedded light emitter as well as methods of manufacturing the same. The light emitter in the senor die is surrounded by a resin. The sensor die is incorporated into semiconductor device packages as well as methods of manufacturing the same. The semiconductor device packages include a first optically transmissive structure on the light sensor of the sensor die and a second optically transmissive structure on the light emitter of the sensor die. The first optically transmissive structure and the second optically transmissive structure cover and protect the light sensor and the light emitter, respectively. A molding compound is on a surface of a sensor die and covers sidewalls of the first and second optically transmissive structures on the sensor die.

公开(公告)号：US20240145258A1

公开(公告)日：2024-05-02

申请号：US18489746

申请日：2023-10-18

Applicant: STMICROELECTRONICS PTE LTD

Inventor： David GANI

IPC: H01L21/56 ,  H01L21/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L21/568 ,  H01L21/02675 ,  H01L23/3142 ,  H01L23/49816 ,  H01L24/05 ,  H01L2224/05013 ,  H01L2224/05023 ,  H01L2924/182 ,  H01L2924/183

Abstract: The present disclosure is directed to at least one semiconductor package including a die within an encapsulant having a first sidewall, an adhesive layer on the encapsulant and having a second sidewall coplanar with the first sidewall of the encapsulant, and an insulating layer on the adhesive layer having a third sidewall coplanar with the first sidewall and the second sidewall. A method of manufacturing the at least one semiconductor package includes forming an insulating layer on a temporary adhesion layer of a carrier, forming an adhesive layer on the insulating layer, and forming a plurality of openings through the adhesive layer and the insulating layer. The plurality of openings through the adhesive layer and the insulating layer may be formed by exposing the adhesive layer and the insulating layer to a laser.

公开(公告)号：US20240036169A1

公开(公告)日：2024-02-01

申请号：US18486071

申请日：2023-10-12

Applicant: STMicroelectronics PTE LTD

Inventor： Jing-En LUAN

IPC: G01S7/481

CPC classification number: G01S7/4813

Abstract: The present disclosure is directed to an optical sensor package with a first assembly and a second assembly with an encapsulant extending between and coupling the first assembly and the second assembly. The first assembly includes a first substrate, a first die on the first substrate, a transparent material on the first die, and an infrared filter on the transparent material. The second assembly includes a second substrate, a second die on the second substrate, a transparent material on the second die, and an infrared filter on the transparent material. Apertures are formed through the encapsulant aligned with the first die and the second die. The first die is configured to transmit light through one aperture, wherein the light reflects off an object to be detected and is received at the second die through another one of the apertures.

公开(公告)号：US20230411332A1

公开(公告)日：2023-12-21

申请号：US18340380

申请日：2023-06-23

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En LUAN

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L23/49816

Abstract: A wafer level chip scale package (WLCSP) with portions that have different thicknesses. A first passive surface of a die in the WLSCP includes a plurality of surfaces. The plurality of surfaces may include inclined surfaces or flat surfaces. Thicker portions of die, with more semiconductor material remaining are non-critical portions that increase a WLCSP's strength for further processing and handling after formation, and the thinner portions are critical portions that reduce a Coefficient of Thermal Expansion (CTE) mismatch between a WLCSP and a PCB.

公开(公告)号：US11821884B2

公开(公告)日：2023-11-21

申请号：US17166580

申请日：2021-02-03

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS PTE LTD

Inventor： Malek Brahem ,  Hatem Majeri ,  Olivier Le Neel ,  Ravi Shankar ,  Enrico Rosario Alessi ,  Pasquale Biancolillo

IPC: G01N33/00 ,  G01N27/12 ,  G01N27/02

CPC classification number: G01N33/0047 ,  G01N27/021 ,  G01N27/12

Abstract: The present disclosure is directed to a gas sensor device that detects gases with large molecules (e.g., a gas with a molecular weight between 150 g/mol and 450 g/mol), such as siloxanes. The gas sensor device includes a thin film gas sensor and a bulk film gas sensor. The thin film gas sensor and the bulk film gas sensor each include a semiconductor metal oxide (SMO) film, a heater, and a temperature sensor. The SMO film of the thin film gas sensor is an thin film (e.g., between 90 nanometers and 110 nanometers thick), and the SMO film of the bulk film gas sensor is an thick film (e.g., between 5 micrometers and 20 micrometers thick). The gas sensor device detects gases with large molecules based on a variation between resistances of the SMO thin film and the SMO thick film.

公开(公告)号：US20230135000A1

公开(公告)日：2023-05-04

申请号：US17962634

申请日：2022-10-10

Applicant: STMicroelectronics Pte Ltd

Inventor： Yean Ching YONG ,  Jianhua JIN ,  Weiyang YAP ,  Voon Cheng NGWAN

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/417 ,  H01L21/765

Abstract: A semiconductor substrate includes: a base substrate layer doped with a first type dopant; a first epitaxial layer on the base substrate layer that has a first thickness and is doped with the first type dopant to provide a first resistivity; a second epitaxial layer on the first epitaxial layer that has a second thickness and is doped with the first type dopant to provide a second resistivity (less than the third resistivity); and a third epitaxial layer on the second epitaxial layer that has a third thickness and is doped with the first type dopant to provide a third resistivity (less than the second resistivity). An oxide field trench transistor includes a trench with insulated polygate and polysource regions extending into the semiconductor substrate and passing through the first doped region, the second doped region, the third epitaxial layer and partially into the second epitaxial layer.