公开(公告)号：US20090302350A1

公开(公告)日：2009-12-10

申请号：US12541763

申请日：2009-08-14

Applicant: Suman Datta ,  Justin K. Brask ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Mantu K. Hudait

Inventor： Suman Datta ,  Justin K. Brask ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Mantu K. Hudait

IPC: H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/7848 ,  Y10S438/933 ,  Y10S438/938

Abstract: Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.

Abstract translation: 描述了增强模式晶体管，其中在源极和漏极区域中使用III-N族化合物以在通道上施加拉伸应变。 源极和漏极区域可以被凸起或嵌入，并且与用于p沟道晶体管的凹陷或凸起的压缩区域一起制造。

公开(公告)号：US20090298266A1

公开(公告)日：2009-12-03

申请号：US12538828

申请日：2009-08-10

Applicant: Mantu K. Hudait ,  Aaron A. Budrevich ,  Dmitri Loubychev ,  Jack T. Kavalieros ,  Suman Datta ,  Joel M. Fastenau ,  Amy W. Liu

Inventor： Mantu K. Hudait ,  Aaron A. Budrevich ,  Dmitri Loubychev ,  Jack T. Kavalieros ,  Suman Datta ,  Joel M. Fastenau ,  Amy W. Liu

IPC: H01L21/20

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02549 ,  H01L21/02584 ,  H01L29/365 ,  H01L29/66462 ,  H01L29/7784

Abstract: A device grade III-V quantum well structure and method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×108 cm−2 to be formed. In an embodiment of the present invention, a delta doped layer is disposed on a dopant segregation barrier in order to confine delta dopant within the delta doped layer and suppress delta dopant surface segregation.

Abstract translation: 描述了器件级III-V量子阱结构及其制造方法。 本发明的实施例能够形成缺陷密度低于1×108cm-2的III-V InSb量子阱器件层。 在本发明的一个实施例中，Δ掺杂层设置在掺杂剂偏析屏障上，以便将δ掺杂剂限制在δ掺杂层内并抑制δ掺杂剂表面偏析。

公开(公告)号：US20090283496A1

公开(公告)日：2009-11-19

申请号：US11391920

申请日：2006-03-28

Applicant: Marko Radosavljevic ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Suman Datta

Inventor： Marko Radosavljevic ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Suman Datta

IPC: B44C1/22 ,  B05D5/12

CPC classification number: B82Y40/00 ,  B82Y30/00 ,  C01B32/162

Abstract: Embodiments of the invention include apparatuses and methods relating to directed carbon nanotube growth using a patterned layer. In some embodiments, the patterned layer includes an inhibitor material that directs the growth of carbon nanotubes.

Abstract translation: 本发明的实施例包括与使用图案化层的定向碳纳米管生长相关的装置和方法。 在一些实施方案中，图案化层包括引导碳纳米管生长的抑制剂材料。

公开(公告)号：US20090267161A1

公开(公告)日：2009-10-29

申请号：US12111714

申请日：2008-04-29

Applicant: Ravi Pillarisetty ,  Jack T. Kavalieros ,  Titash Rakshit ,  Gilbert Dewey ,  Willy Rachmady

Inventor： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Titash Rakshit ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L29/66545 ,  H01L29/66795

Abstract: Techniques and structures for increasing body dopant uniformity in multi-gate transistor devices are generally described. In one example, an electronic device includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate region is disposed between the source region and the drain region, the gate region being body-doped after a sacrificial gate structure is removed from the multi-gate fin and before a subsequent gate structure is formed, a dielectric material coupled with the source region and the drain region of the multi-gate fin, and the subsequent gate structure coupled to the gate region of the multi-gate fin.

Abstract translation: 通常描述用于增加多栅极晶体管器件中的体掺杂物均匀性的技术和结构。 在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的多栅极鳍片，多栅极鳍片，包括源极区域，漏极区域和栅极区域，其中栅极区域设置在源极 区域和漏极区域，在从多栅极鳍去除牺牲栅极结构之后并且在形成后续栅极结构之后，栅极区域被体掺杂，与多层栅极的源极区域和漏极区域耦合的介电材料 并且随后的栅极结构耦合到多栅极鳍的栅极区域。

公开(公告)号：US07592213B2

公开(公告)日：2009-09-22

申请号：US11323688

申请日：2005-12-29

Applicant: Suman Datta ,  Justin K. Brask ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Mantu K. Hudait

Inventor： Suman Datta ,  Justin K. Brask ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Mantu K. Hudait

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/7848 ,  Y10S438/933 ,  Y10S438/938

Abstract: Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.

Abstract translation: 描述了增强模式晶体管，其中在源极和漏极区域中使用III-N族化合物以在通道上施加拉伸应变。 源极和漏极区域可以被凸起或嵌入，并且与用于p沟道晶体管的凹陷或凸起的压缩区域一起制造。

公开(公告)号：US07569869B2

公开(公告)日：2009-08-04

申请号：US11729564

申请日：2007-03-29

Applicant: Been-Yih Jin ,  Robert S. Chau ,  Suman Datta ,  Jack T. Kavalieros ,  Marko Radosavlievic

Inventor： Been-Yih Jin ,  Robert S. Chau ,  Suman Datta ,  Jack T. Kavalieros ,  Marko Radosavlievic

IPC: H01L29/737 ,  H01L29/778

CPC classification number: H01L29/1054 ,  H01L29/517 ,  H01L29/7787 ,  H01L29/7843 ,  H01L29/7851

Abstract: A transistor structure and a system including the transistor structure. The transistor structure comprises: a substrate including a first layer comprising a first crystalline material; a tensile strained channel formed on a surface of the first layer and comprising a second crystalline material having a lattice spacing that is smaller than a lattice spacing of the first crystalline material; a metal gate on the substrate; a pair of sidewall spacers on opposite sides of the metal gate; and a source region and a drain region on opposite sides of the metal gate adjacent a corresponding one of the sidewall spacers.

Abstract translation: 晶体管结构和包括晶体管结构的系统。 晶体管结构包括：衬底，其包括包含第一晶体材料的第一层; 形成在所述第一层的表面上的拉伸应变通道，并且包括晶格间距小于所述第一结晶材料的晶格间距的第二结晶材料; 基板上的金属栅极; 在金属门的相对侧上的一对侧壁间隔件; 以及在金属栅极的与相应的一个侧壁间隔物相邻的相对侧上的源极区域和漏极区域。

公开(公告)号：US07566605B2

公开(公告)日：2009-07-28

申请号：US11395939

申请日：2006-03-31

Applicant: Lucian Shifren ,  Jack T. Kavalieros ,  Steven M. Cea ,  Cory E. Weber ,  Justin K. Brask

Inventor： Lucian Shifren ,  Jack T. Kavalieros ,  Steven M. Cea ,  Cory E. Weber ,  Justin K. Brask

IPC: H01L21/8238 ,  H01L21/425

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7846 ,  H01L29/7848

Abstract: A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed.

公开(公告)号：US20090140341A1

公开(公告)日：2009-06-04

申请号：US11948414

申请日：2007-11-30

Applicant: Ravi Pillarisetty ,  Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle

Inventor： Ravi Pillarisetty ,  Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L27/1104 ,  H01L27/0207 ,  H01L27/11 ,  H01L29/785

Abstract: Independent n-tips for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) devices coupled with the semiconductor fin, the one or more PD devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PD devices, and one or more multi-gate pass gate (PG) devices coupled with the semiconductor fin, the one or more PG devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PG devices, wherein the n-tip dopant concentration for the PG device is lower than the n-tip dopant concentration for the PD device.

Abstract translation: 通常描述多栅极晶体管的独立n尖端。 在一个示例中，设备包括半导体鳍片，与半导体鳍片耦合的一个或多个多栅极下拉（PD）器件，所述一个或多个PD器件在与半导体鳍片材料相邻的半导体鳍片材料中具有n端掺杂剂浓度 一个或多个PD器件，以及与半导体鳍片耦合的一个或多个多栅极通过栅极（PG）器件，所述一个或多个PG器件在与所述一个或多个PG相邻的半导体鳍片材料中具有n尖端掺杂剂浓度 器件，其中PG器件的n尖掺杂剂浓度低于PD器件的n尖掺杂剂浓度。

公开(公告)号：US07521775B2

公开(公告)日：2009-04-21

申请号：US11452883

申请日：2006-06-13

Applicant: Brian S. Doyle ,  Uday Shah ,  Been-Yih Jin ,  Jack T. Kavalieros

Inventor： Brian S. Doyle ,  Uday Shah ,  Been-Yih Jin ,  Jack T. Kavalieros

IPC: H01L29/06

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide.

Abstract translation: 本发明的实施例包括与具有高k电介质的三维晶体管和金属栅极相关的装置和方法，其翅​​片由其顶表面上的硬掩模层保护。 在一个实施例中，硬掩模层包括氧化物。

公开(公告)号：US20090095984A1

公开(公告)日：2009-04-16

申请号：US12338839

申请日：2008-12-18

Applicant: Justin K. Brask ,  Suman Datta ,  Mark L. Doczy ,  James M. Blackwell ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Robert S. Chau

Inventor： Justin K. Brask ,  Suman Datta ,  Mark L. Doczy ,  James M. Blackwell ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/28 ,  H01L29/20

CPC classification number: H01L21/314 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28008 ,  H01L21/3141 ,  H01L21/31616 ,  H01L21/31645 ,  H01L29/2003 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7784

Abstract: A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.

Abstract translation: 描述了III-V族半导体器件及其制造方法。 高k电介质通过硫族化物区域连接到约束区域。