公开(公告)号：US20230325649A1

公开(公告)日：2023-10-12

申请号：US17847486

申请日：2022-06-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Mark Reiten

IPC: G06N3/063 ,  G06F17/16

CPC classification number: G06N3/0635 ,  G06F17/16

Abstract: Numerous examples are disclosed of an artificial neural network that comprises vector-by-matrix multiplication arrays utilizing analog inputs. In one example, a system comprises a vector by matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, a capacitor comprising a first terminal and a second terminal, the second terminal coupled to a common potential, a row decoder to enable an application of an input signal to the first terminal of the capacitor in response to an address, and a buffer coupled to the first terminal of the capacitor, the buffer to generate an output voltage for a respective row of the vector by matrix multiplication array.

公开(公告)号：US20230325645A1

公开(公告)日：2023-10-12

申请号：US17848371

申请日：2022-06-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Mark Reiten ,  Nhan Do

IPC: G06N3/063 ,  G06F17/16

CPC classification number: G06N3/063 ,  G06F17/16

Abstract: Numerous examples are disclosed of an artificial neural network comprising a three-dimensional integrated circuit. In one embodiment, a three-dimensional integrated circuit for use in an artificial neural network comprises a first die comprising a first vector by matrix multiplication array and a first input multiplexor, the first die located on a first vertical layer; a second die comprising an input circuit, the second die located on a second vertical layer different than the first vertical layer; and one or more vertical interfaces coupling the first die and the second die; wherein during a read operation, the input circuit provides an input signal to the first input multiplexor over at least one of the one or more vertical interfaces, the first input multiplexor applies the input signal to one or more rows in the first vector by matrix multiplication array, and the first vector by matrix multiplication array generates an output.

公开(公告)号：US20230306246A1

公开(公告)日：2023-09-28

申请号：US17724415

申请日：2022-04-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G06N3/063

CPC classification number: G06N3/063

Abstract: Numerous examples are disclosed for performing calibration of various electrical parameters in a deep learning artificial neural network. In one example, a method comprises adjusting a bias voltage applied to one or more non-volatile memory cells in an artificial neural network, performing a performance target check on the one or more non-volatile memory cells in the artificial neural network, and repeating the adjusting and performing until the performance target check indicates an electrical parameter is within a predetermined range.

公开(公告)号：US20230292504A1

公开(公告)日：2023-09-14

申请号：US17834746

申请日：2022-06-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Zhuoqiang Jia ,  Leo Xing ,  Xian Liu ,  Serguei Jourba ,  Nhan Do

IPC: H01L27/11531 ,  H01L29/423 ,  H01L21/28 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L27/11531 ,  H01L29/42328 ,  H01L29/40114 ,  H01L29/7883 ,  H01L29/66825

Abstract: A method includes recessing an upper surface of a substrate in first and second areas relative to a third area, forming a first conductive layer in the first area, forming a second conductive layer in the three areas, selectively removing the first and second conductive layers in the first area, while maintaining the second conductive layer in the second and third areas, leaving pairs of stack structures in the first area respectively having a control gate of the second conductive layer and a floating gate of the first conductive layer, forming a third conductive layer in the three areas, recessing the upper surface of the third conductive layer below tops of the stack structures and removing the third conductive layer from the second and third areas, removing the second conductive layer from the second and third areas, and forming blocks of metal material in the second and third areas.

公开(公告)号：US20230290864A1

公开(公告)日：2023-09-14

申请号：US17824812

申请日：2022-05-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/788 ,  H01L29/423 ,  H01L29/78 ,  H01L27/11556

CPC classification number: H01L29/66795 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823412 ,  H01L29/0847 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/42328 ,  H01L29/7851 ,  H01L27/11556

Abstract: A method of forming a device on a silicon substrate having first, second and third areas includes recessing an upper substrate surface in the first and third areas, forming an upwardly extending silicon fin in the second area, forming first source, drain and channel regions in the first area, forming second source, drain and channel regions in the fin, forming third source, drain and channel regions in the third area, forming a floating gate over a first portion of the first channel region using a first polysilicon deposition, forming an erase gate over the first source region and a device gate over the third channel region using a second polysilicon deposition, and forming a word line gate over a second portion of the first channel region, a control gate over the floating gate, and a logic gate over the second channel region using a metal deposition.

公开(公告)号：US11727989B2

公开(公告)日：2023-08-15

申请号：US17734807

申请日：2022-05-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  G06N3/08 ,  H01L29/788 ,  H10B41/30 ,  G06N3/045

CPC classification number: G11C16/0425 ,  G06N3/08 ,  H01L29/7883 ,  H01L29/7885 ,  H10B41/30 ,  G06N3/045

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. In one example, a method for programming a plurality of non-volatile memory cells in an array of non-volatile memory cells, comprises generating a high voltage, and programming a plurality of non-volatile memory cells in an array using the high voltage when a programming enable signal is asserted and providing a feedback loop to maintain the high voltage while programming the plurality of non-volatile memory cells.

公开(公告)号：US20230252276A1

公开(公告)日：2023-08-10

申请号：US17727650

申请日：2022-04-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G06N3/063 ,  G06F17/12 ,  H03M1/14

CPC classification number: G06N3/0635 ,  G06F17/12 ,  H03M1/142

Abstract: Numerous examples are disclosed for performing calibration of various electrical parameters in a deep learning artificial neural network. In one example, a system comprises a digital-to-analog converter for receiving an input of k bits and generating a first analog output, a mapping scalar for converting the first analog output into a second analog output, and an analog-to-digital converter for generating an output of n bits from the second analog output, where n is a different value than k.

公开(公告)号：US20230178147A1

公开(公告)日：2023-06-08

申请号：US18103383

申请日：2023-01-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari

IPC: G11C11/54 ,  G11C16/04 ,  G06N3/063 ,  G11C16/26 ,  G11C16/28 ,  H03F3/00 ,  H03M1/16 ,  G06N3/065

CPC classification number: G11C11/54 ,  G11C16/0425 ,  G06N3/063 ,  G11C16/26 ,  G11C16/0416 ,  G11C16/28 ,  H03F3/005 ,  H03M1/164 ,  G06N3/065 ,  H03M1/38

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, a system comprises a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W+ values, and wherein one of the columns in the first array is a dummy column; and a second array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W− values, and wherein one of the columns in the second array is a dummy column; wherein pairs of cells from the first array and the second array store a differential weight, W, according to the formula W=(W+)−(W−).

公开(公告)号：US20230154528A1

公开(公告)日：2023-05-18

申请号：US17585452

申请日：2022-01-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G11C11/54 ,  G06N3/063 ,  G11C16/26 ,  G11C16/10 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C11/54 ,  G06N3/063 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/0425 ,  H01L27/11521

Abstract: Numerous embodiments for improving an analog neural memory in a deep learning artificial neural network as to accuracy or power consumption as temperature changes are disclosed. In some embodiments, a method is performed to determine in real-time a bias value to apply to one or more memory cells in a neural network. In other embodiments, a bias voltage is determined from a lookup table and is applied to a terminal of a memory cell during a read operation.

公开(公告)号：US20230141943A1

公开(公告)日：2023-05-11

申请号：US17585261

申请日：2022-01-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Kha Nguyen ,  Hien Pham ,  Duc Nguyen

IPC: G11C16/16 ,  G11C16/10 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/16 ,  G11C16/102 ,  G11C16/30 ,  G11C16/26

Abstract: Numerous embodiments of a transceiver for providing high voltages for use during erase or program operations in a non-volatile memory system are disclosed. In one embodiment, a transceiver comprises a PMOS transistor and a native NMOS transistor. In another embodiment, a transceiver comprises a PMOS transistor, an NMOS transistor, and a native NMOS transistor.