公开(公告)号：US20160181323A1

公开(公告)日：2016-06-23

申请号：US15056548

申请日：2016-02-29

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2454 ,  H01L27/11553 ,  H01L27/1158 ,  H01L27/2481 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L45/1608

Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

Abstract translation: 各种实施例包括诸如具有连续单元柱的存储器堆叠的装置和方法。 在各种实施例中，该装置包括源材料，缓冲材料，选择栅极漏极（SGD）以及布置在源材料和SGD之间的存储器堆叠。 存储器堆叠包括交替电平的导体材料和电介质材料。 连续的通道填充材料形成从源材料连续到至少与SGD相对应的水平的细胞柱。

公开(公告)号：US20160148949A1

公开(公告)日：2016-05-26

申请号：US15013298

申请日：2016-02-02

Applicant: Micron Technology, Inc.

Inventor： Srikant Jayanti ,  Fatma Arzum Simsek-Ege ,  Pavan Kumar Reddy Aella

IPC: H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/8239 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/04 ,  H01L29/16 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7889 ,  H01L29/7926

Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

Abstract translation: 半导体结构可以包括交替的电介质材料和控制栅极的堆叠，与控制栅极横向相邻的电荷存储结构，每个电荷存储结构和横向相邻的控制栅之间的电荷块材料，以及延伸穿过堆叠 交替氧化物和控制门。 堆叠中的每个介电材料具有不同密度和/或不同的去除速率的至少两个部分。 还公开了制造这种半导体结构的方法。

公开(公告)号：US20160133752A1

公开(公告)日：2016-05-12

申请号：US14987147

申请日：2016-01-04

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Darwin Franseda Fan ,  Fatma Arzum Simsek-Ege ,  James Brighten ,  Aurelio Giancarlo Mauri ,  Srikant Jayanti

IPC: H01L29/788 ,  H01L27/115

CPC classification number: H01L29/7887 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7881 ,  H01L29/7889

Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

公开(公告)号：US09230986B2

公开(公告)日：2016-01-05

申请号：US14610755

申请日：2015-01-30

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Darwin Franseda Fan ,  Fatma Arzum Simsek-Ege ,  James Brighten ,  Aurelio Giancarlo Mauri ,  Srikant Jayanti

IPC: H01L29/788 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/7887 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7881 ,  H01L29/7889

Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

公开(公告)号：US08946076B2

公开(公告)日：2015-02-03

申请号：US13835551

申请日：2013-03-15

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Aaron R. Wilson

IPC: H01L21/302 ,  H01L27/115 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/033

CPC classification number: H01L27/11578 ,  H01L21/0334 ,  H01L21/0335 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31144 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7889

Abstract: Some embodiments include methods of forming vertically-stacked memory cells. An opening is formed to extend partially through a stack of alternating electrically insulative levels and electrically conductive levels. A liner is formed along sidewalls of the opening, and then the stack is etched to extend the opening. The liner is at least partially consumed during the etch and forms passivation material. Three zones occur during the etch, with one of the zones being an upper zone of the opening protected by the liner, another of the zones being an intermediate zone of the opening protected by passivation material but not the liner, and another of the zones being a lower zone of the opening which is not protected by either passivation material or the liner. Cavities are formed to extend into the electrically conductive levels along sidewalls of the opening. Charge blocking dielectric and charge-storage structures are formed within the cavities.

Abstract translation: 一些实施例包括形成垂直堆叠的存储器单元的方法。 形成开口部分地延伸通过交替的电绝缘水平和导电水平的堆叠。 沿着开口的侧壁形成衬垫，然后蚀刻叠层以延伸开口。 在蚀刻期间衬垫至少部分消耗，并形成钝化材料。 在蚀刻期间发生三个区域，其中一个区域是由衬垫保护的开口的上部区域，另一个区域是由钝化材料而不是衬垫保护的开口的中间区域，另一个区域是 开口的下部区域不被钝化材料或衬垫保护。 腔体形成为延伸到沿开口侧壁的导电水平。 电荷阻挡电介质和电荷存储结构形成在空腔内。

公开(公告)号：US08778762B2

公开(公告)日：2014-07-15

申请号：US13708789

申请日：2012-12-07

Applicant: Micron Technology, Inc.

Inventor： Saurabh Keshav ,  Scott Pook ,  Fatma Arzum Simsek-Ege

IPC: H01L21/336

CPC classification number: H01L29/66833 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

Abstract: Some embodiments include methods of forming vertically-stacked structures, such as vertically-stacked memory cells. A first hardmask is formed over a stack of alternating electrically conductive levels and electrically insulative levels. A first opening is formed through the first hardmask and the stack. Cavities are formed to extend into the electrically conductive levels. A fill material is formed within the first opening and within the cavities. A second hardmask is formed over the first hardmask and over the fill material. A second opening is formed through the second hardmask. The second opening is narrower than the first opening. The second opening is extended into the fill material to form an upwardly-opening container from the fill material. Sidewalls of the upwardly-opening container are removed, while leaving the fill material within the cavities as a plurality of vertically-stacked structures.

Abstract translation: 一些实施例包括形成垂直堆叠结构的方法，例如垂直堆叠的存储单元。 第一个硬掩模形成在交替导电水平和电绝缘水平的叠层上。 通过第一硬掩模和堆叠形成第一开口。 形成腔以延伸到导电水平。 填充材料形成在第一开口内并在空腔内。 在第一个硬掩模和填充材料上形成第二个硬掩模。 通过第二硬掩模形成第二个开口。 第二个开口比第一个开口窄。 第二开口延伸到填充材料中以从填充材料形成向上开口的容器。 去除向上开口的容器的侧壁，同时将填充材料留在空腔内作为多个垂直堆叠的结构。