公开(公告)号：US06982463B2

公开(公告)日：2006-01-03

申请号：US10450009

申请日：2001-11-26

Applicant: Armand Castillejo

Inventor： Armand Castillejo

IPC: H01L23/62

CPC classification number: H01L23/10 ,  H01L23/585 ,  H01L23/60 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

Abstract: The integrated circuit includes a substrate SB incorporating a plurality of electronic components C1, C2 and a seal ring SR around the electronic components. It includes cold spot means VM, PG, BDG disposed between the electronic components and the seal ring. It further includes electrostatic discharge protection means including an electrostatic discharge rail VM around the electronic components and constituting said cold spot means.

Abstract translation: 集成电路包括在电子部件周围包括多个电子部件C 1，C 2和密封环SR的基板SB。 它包括设置在电子部件和密封环之间的冷点装置VM，PG，BDG。 还包括静电放电保护装置，其包括电子部件周围的静电放电轨VM，构成所述冷点装置。

公开(公告)号：US06972497B2

公开(公告)日：2005-12-06

申请号：US10359049

申请日：2003-02-05

Applicant: Christophe Prior

Inventor： Christophe Prior

IPC: H01L23/28 ,  H01L23/34 ,  H01L31/0203 ,  H01L31/0232 ,  H01L31/18

CPC classification number: H04N5/2254 ,  H01L27/14618 ,  H01L27/14625 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An optical semiconductor product includes an integrated circuit chip having an optical sensor in its front face. The chip is attached to a support plate and electrical interconnection is made therebetween. A protective ring is fastened to the front face of the chip, around and at some distance from the optical sensor. A ring of encapsulating material is deposited to surround the periphery of the chip and lie between the front face of the support plate (2) and the protective ring.

Abstract translation: 光学半导体产品包括在其正面具有光学传感器的集成电路芯片。 芯片连接到支撑板，并且在它们之间形成电互连。 保护环紧固在芯片的前表面上，距离光学传感器约一定距离。 沉积环形密封材料环绕芯片的周边并位于支撑板（2）的前表面和保护环之间。

公开(公告)号：US06972451B2

公开(公告)日：2005-12-06

申请号：US10437633

申请日：2003-05-14

Applicant: Philippe Delpech ,  Sébastien Cremer ,  Michel Marty

Inventor： Philippe Delpech ,  Sébastien Cremer ,  Michel Marty

IPC: H01L21/02 ,  H01L23/522 ,  H01L27/108 ,  H01L21/20

CPC classification number: H01L28/92 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor formed in a substrate including a recess dug into a substrate; a first layer of a dielectric material covering the walls, the bottom and the edges of the recess; a second layer of a conductive material covering the first layer; a third layer of a conductive or insulating material filling the recess; trenches crossing the third layer; a fourth layer of a conductive material covering the walls, the bottoms as well as the intervals between these trenches and the edges thereof; a fifth layer of a dielectric material covering the fourth layer; and a sixth layer of a conductive material covering the fifth layer.

Abstract translation: 一种电容器，其形成在基板中，该基板包括挖入基板的凹部; 覆盖所述壁，所述凹部的底部和边缘的电介质材料的第一层; 覆盖第一层的导电材料的第二层; 填充所述凹部的导电或绝缘材料的第三层; 穿越第三层的沟槽; 覆盖壁的第四层导电材料，底部以及这些沟槽与其边缘之间的间隔; 覆盖第四层的电介质材料的第五层; 以及覆盖第五层的导电材料的第六层。

公开(公告)号：US06969661B2

公开(公告)日：2005-11-29

申请号：US10744680

申请日：2003-12-23

Applicant: Aomar Halimaoui ,  Daniel Bensahel

Inventor： Aomar Halimaoui ,  Daniel Bensahel

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L29/51 ,  H01L21/3205

CPC classification number: H01L21/28194 ,  H01L21/31604 ,  H01L21/31691 ,  H01L29/517 ,  H01L29/66583

Abstract: A method for forming, in an integrated circuit, a localized region of a material difficult to etch, including the steps of forming a first silicon oxide layer having a thickness smaller than 1 nm on a silicon substrate; depositing, on the first layer, a second layer selectively etchable with respect to the first layer; forming in the second layer an opening according to the pattern of said localized region; selectively growing on the second layer, around the opening, a germanium layer, the material of the second layer being chosen to enable this selective growth, whereby there exists in the germanium an opening conformable with the above opening; depositing the material difficult to etch so that it does not deposit on the germanium; depositing a conductive layer to fill the opening in the germanium; performing a leveling to expose the germanium; and removing the germanium and the first and second layers.

公开(公告)号：US06967356B2

公开(公告)日：2005-11-22

申请号：US10169852

申请日：2001-10-11

Applicant: Gérard Auriel

Inventor： Gérard Auriel

IPC: H01L29/08 ,  H01L29/747 ,  H01L29/74 ,  H01L31/111

CPC classification number: H01L29/0834 ,  H01L29/747

Abstract: The invention concerns a vertical component with a four-layered structure comprising a thick lightly-doped zone (1) of a first type of conductivity providing the component voltage strength, enclosed with a peripheral wall (2) of a second type of conductivity extending vertically from one surface to the other of the component, and highly doped layer (3) of the second type of conductivity extending over the entire rear surface of the component. A lightly-doped layer (21) of the second type of conductivity extends over the entire surface of the component at the interface between the lightly-doped thick zone of the first type of conductivity and the highly-doped layer of the second type of conductivity.

Abstract translation: 本发明涉及具有四层结构的垂直分量，其包括提供元件电压强度的第一类导电性的厚的轻掺杂区（1），所述第一类型的导电性区域（1）由垂直延伸的第二导电类型的周向壁（2）包围 从组件的一个表面到另一个，以及在组件的整个后表面上延伸的第二类导电体的高掺杂层（3）。 第二类导电性的轻掺杂层（21）在第一类导电性的轻掺杂厚区与第二导电类型的高掺杂层之间的界面处在该元件的整个表面上延伸 。

公开(公告)号：US06961891B2

公开(公告)日：2005-11-01

申请号：US09960835

申请日：2001-09-21

Applicant: Laurent Murillo

Inventor： Laurent Murillo

IPC: H03M13/13 ,  H03M13/15 ,  H03M13/19 ,  H03M13/29

CPC classification number: H03M13/19 ,  H03M13/6502

Abstract: A method for determining r error detection bits of a word of m bits to be coded, including the step of calculating the product of a vector with m components representative of said word of m bits to be coded and of a parity check matrix. The parity check matrix includes a pattern matrix that may be repeated in said parity check matrix, and said pattern being chosen so that a sum modulo 2 of any two columns of said sub-matrix does not give as a result another column of said sub-matrix. Another method determines a syndrome using r error detection bits determined by the above method.

Abstract translation: 一种用于确定要编码的m比特字的r个错误检测比特的方法，包括计算具有代表要编码的所述m比特字的m个分量的向量的乘积和奇偶校验矩阵的步骤。 奇偶校验矩阵包括可以在所述奇偶校验矩阵中重复的模式矩阵，并且所述模式被选择为使得所述子矩阵的任意两列的模2的和号不给出所述子矩阵的另一列， 矩阵。 另一种方法使用由上述方法确定的r个误差检测位来确定综合征。

公开(公告)号：US06960985B2

公开(公告)日：2005-11-01

申请号：US09770783

申请日：2001-01-26

Applicant: Luc Wuidart

Inventor： Luc Wuidart

IPC: G06K17/00 ,  G01S13/75 ,  G01S13/76 ,  G01S13/79 ,  G06K7/00 ,  H02J17/00 ,  H04B1/59 ,  H04B5/02 ,  H04Q1/00

CPC classification number: G06K7/10217 ,  G06K7/0008

Abstract: A terminal for generating an electromagnetic field adapted to cooperating with at least one transponder when the latter enters its field and including an oscillating circuit adapted to receiving a high-frequency A.C. excitation voltage, circuitry for regulating the signal phase in the oscillating circuit with respect to a reference value, circuitry for determining an instantaneous information relative to the magnetic coupling between the transponder and the terminal, and circuitry for adapting the electromagnetic field power according to at least said present information.

Abstract translation: 一种用于产生电磁场的终端，其适于在后者进入其场期间与至少一个应答器协作并且包括适于接收高频AC激励电压的振荡电路，用于调节振荡电路中的信号相位相对于 参考值，用于确定相对于应答器和终端之间的磁耦合的瞬时信息的电路，以及根据至少所述当前信息调整电磁场功率的电路。

公开(公告)号：US06952242B2

公开(公告)日：2005-10-04

申请号：US09881892

申请日：2001-06-15

Applicant: Olivier Le Briz ,  Olivier Scouarnec ,  Corinne Ianigro

Inventor： Olivier Le Briz ,  Olivier Scouarnec ,  Corinne Ianigro

IPC: H04N3/233 ,  H04N9/28 ,  H04N9/31

CPC classification number: H04N3/2335 ,  H04N9/28

Abstract: A control signal for controlling a correction circuit for at least one electron beam that scans a screen line by line, the amplitude of which varies along each line according to a curve of a first type determined by line parameters, each of the line parameters varying, from one line to another, according to a curve of the first type determined by column parameters.

Abstract translation: 一种用于控制至少一根电子束的校正电路的控制信号，其逐行扫描屏幕，其幅度根据由线路参数确定的第一类型的曲线沿着每一行变化，每个线路参数变化， 从一行到另一行，根据由列参数确定的第一种类型的曲线。

公开(公告)号：US20050212967A1

公开(公告)日：2005-09-29

申请号：US11086808

申请日：2005-03-22

Applicant: Nicolas Quesne

Inventor： Nicolas Quesne

IPC: H04N5/14 ,  H04N5/44 ,  H04N5/45 ,  H04N5/76 ,  H04N5/765 ,  H04N5/775 ,  H04N5/783 ,  H04N5/85 ,  H04N5/907 ,  H04N9/64 ,  H04N9/804

CPC classification number: H04N5/76 ,  H04N5/14 ,  H04N5/4448 ,  H04N5/45 ,  H04N5/765 ,  H04N5/783 ,  H04N5/85 ,  H04N5/907 ,  H04N7/0132 ,  H04N9/641 ,  H04N9/8042 ,  H04N21/42692 ,  H04N21/4316 ,  H04N21/4333 ,  H04N21/440281 ,  H04N21/47217

Abstract: In order to display moving images, an input receives a video signal transporting video images. A user interface receives commands input by a user. An input video subsystem continuously generates a first stream of video images on the basis of the input video signal. At least one volatile storage unit stores a sequence of images extracted from the first stream of images, either continuously, or in response to a “record” command given by the user. An output video subsystem generates and displays a second stream of images on the basis selectively of: the first stream of video images, the stored sequence of images, or a combination of the two, in response to an appropriate read command input by the user via the user interface.

Abstract translation: 为了显示运动图像，输入接收传送视频图像的视频信号。 用户接口接收用户输入的命令。 输入视频子系统基于输入视频信号连续生成第一视频图像流。 至少一个易失性存储单元连续地或者响应于用户给出的“记录”命令存储从第一图像流中提取的图像序列。 输出视频子系统响应于用户输入的适当的读取命令，选择性地生成并显示第二图像流，所述第二图像流是：视频图像的第一流，存储的图像序列或两者的组合， 用户界面。

公开(公告)号：US06946825B2

公开(公告)日：2005-09-20

申请号：US10682702

申请日：2003-10-09

Applicant: Davide Tesi

Inventor： Davide Tesi

IPC: G05F3/30 ,  G05F3/16

CPC classification number: G05F3/30

Abstract: A circuit for generating a reference voltage of bandgap type. The circuit includes a current mirror assembly of cascode type including, from a high supply rail, at least two parallel branches of P-channel MOS transistors. The circuit also includes a bipolar assembly in series with one of the branches of the mirror assembly down to a low supply rail, formed of two parallel branches each including, in series, a diode-connected bipolar transistor and, respectively, one resistor and two resistors. The circuit also includes a differential amplifier for balancing the currents in the two branches of the bipolar assembly, the reference voltage being provided by the terminal of interconnection of the mirror assembly with the bipolar assembly.

Abstract translation: 一种产生带隙型参考电压的电路。 该电路包括共源共栅型的电流镜组件，其包括来自高电源轨的P沟道MOS晶体管的至少两个平行分支。 该电路还包括与反射镜组件的一个支路串联连接到低电源轨的双极组件，其由两个并联的分支组成，每个并联支路串联连接二极管连接的双极晶体管，分别包括一个电阻器和两个 电阻 电路还包括用于平衡双极组件的两个分支中的电流的差分放大器，参考电压由反射镜组件与双极组件的互连端子提供。