公开(公告)号：US08760910B2

公开(公告)日：2014-06-24

申请号：US13972455

申请日：2013-08-21

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Gurtej S. Sandhu

IPC: G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  G11C13/00 ,  G11C7/18 ,  G11C11/4097

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/18 ,  G11C11/4097 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/71 ,  G11C2213/78 ,  H01L27/0688 ,  H01L27/101

Abstract: An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.

Abstract translation: 垂直堆叠层的非易失性交叉点存储单元的阵列包括在存储单元的各个层内的多个水平取向的字线。 具有局部垂直位线延伸的多个水平定向的全局位线延伸穿过多个层。 存储单元的个体包括在水平定向的字线之一和本地垂直位线延伸之一中的一个之间接收的多电阻状态材料，其中这些交叉具有这样的交叉的单个存储器单元的相对的导电电极。 多个位线选择电路单独地电和物理地连接到本地垂直位线延伸的个体，并且被配置为向全局水平位线的个体提供电压电位。 公开了其它实施例和方面。

公开(公告)号：US20140097435A1

公开(公告)日：2014-04-10

申请号：US14101041

申请日：2013-12-09

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang

IPC: H01L27/115

CPC classification number: H01L27/11524 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include NAND memory constructions. The constructions may contain semiconductor material pillars extending upwardly between dielectric regions, with individual pillars having a pair of opposing vertically-extending sides along a cross-section. First conductivity type regions may be along first sides of the pillars, and second conductivity type regions may be along second sides of the individual pillars; with the second conductivity type regions contacting interconnect lines. Vertical NAND strings may be over the pillars, and select devices may selectively couple the NAND strings with the interconnect lines. The select devices may have vertical channels directly against the semiconductor material pillars and directly against upper regions of the first and second conductivity type regions. Some embodiments include methods of forming NAND memory constructions.

Abstract translation: 一些实施例包括NAND存储器结构。 这些结构可以包含在电介质区域之间向上延伸的半导体材料柱，其中单独的柱具有沿着横截面的一对相对的垂直延伸的侧面。 第一导电类型区域可以沿着柱的第一侧，并且第二导电类型区域可以沿着各个柱的第二侧; 第二导电类型区域接触互连线。 垂直NAND串可以在柱上，并且选择装置可以选择性地将NAND串与互连线耦合。 选择装置可以具有直接抵靠半导体材料柱的垂直通道并且直接抵靠第一和第二导电类型区域的上部区域。 一些实施例包括形成NAND存储器结构的方法。

公开(公告)号：US08669144B2

公开(公告)日：2014-03-11

申请号：US13939082

申请日：2013-07-10

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Janos Fucsko

IPC: H01L21/82

CPC classification number: H01L21/768 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/228 ,  H01L27/24

Abstract: Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.

Abstract translation: 一些实施例包括形成存储器阵列的方法。 一叠半导体材料板可以被图案化以将该板细分成多个。 导电层可以沿着片的侧壁边缘形成。 然后将这些片材图案化成线阵列，阵列具有垂直列和水平行。 单独的线可以具有连接到导电层的第一端，可以具有与第一端相对的第二端，并且可以在第一端和第二端之间具有中间区域。 栅极材料可以沿着中间区域形成。 存储单元结构可以形成在电线的第二端。 多个垂直延伸的电互连可以通过存储单元结构连接到导线，其中各个垂直延伸的电互连沿阵列的各个列。 一些实施例包括并入到集成电路中的存储器阵列。

公开(公告)号：US20140057398A1

公开(公告)日：2014-02-27

申请号：US14066811

申请日：2013-10-30

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang

IPC: H01L29/66 ,  H01L21/8229

CPC classification number: H01L29/66386 ,  H01L21/8229 ,  H01L27/1027 ,  H01L27/105 ,  H01L27/11 ,  H01L29/74 ,  H01L29/94

Abstract: A memory cell includes a thyristor having a plurality of alternately doped, vertically superposed semiconductor regions; a vertically oriented access transistor having an access gate; and a control gate operatively laterally adjacent one of the alternately doped, vertically superposed semiconductor regions. The control gate is spaced laterally of the access gate. Other embodiments are disclosed, including methods of forming memory cells and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor.

Abstract translation: 存储单元包括具有多个交替掺杂的垂直叠加的半导体区域的晶闸管; 具有存取栅极的垂直取向的存取晶体管; 以及控制门，其操作地横向地邻近交替掺杂的垂直叠加的半导体区域中的一个。 控制门在接入门侧面隔开。 公开了其它实施例，包括形成存储器单元的方法和形成垂直取向晶闸管和垂直取向的存取晶体管的共用掺杂半导体区域的方法。

公开(公告)号：US20140035015A1

公开(公告)日：2014-02-06

申请号：US14043476

申请日：2013-10-01

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Mike N. Nguyen

IPC: H01L27/108

CPC classification number: H01L27/10802 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/7841

Abstract: An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.

Abstract translation: 公开了一种具有浮体的存储单元的装置。 存储单元可以包括绝缘层上的晶体管，晶体管包括源极和漏极。 存储单元还可以包括浮动体，其包括位于源极和漏极之间的第一区域，远离源极和漏极中的每一个定位的第二区域，以及延伸穿过绝缘层并且将第一区域耦合到第二区域的第二区域 地区。 另外，存储单元可以包括至少部分地围绕第二区域并被配置为可操作地耦合到偏置电压的偏置栅极。 此外，存储单元可以包括多个电介质层，其中第二区域的每个外部垂直表面具有与其相邻的多个电介质层。

公开(公告)号：US20140030856A1

公开(公告)日：2014-01-30

申请号：US14041928

申请日：2013-09-30

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H01L21/768

CPC classification number: H01L27/11582 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C2213/71 ,  H01L21/28273 ,  H01L21/76838 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L45/06

Abstract: Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

Abstract translation: 一些实施例包括存储器件和形成存储器件的方法。 一个这样的存储器件包括第一组存储器单元，第一组的每个存储器单元形成在位于存储器件的一个器件级中的第一控制栅极的空腔中。 存储器件还包括第二组存储器单元，第二组的每个存储器单元形成在位于存储器件的另一个器件级中的第二控制栅极的腔中。 描述附加的装置和方法。

公开(公告)号：US20130295737A1

公开(公告)日：2013-11-07

申请号：US13933854

申请日：2013-07-02

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H01L29/66

CPC classification number: H01L21/762 ,  H01L21/32 ,  H01L27/0814 ,  H01L27/108 ,  H01L27/10808 ,  H01L27/2454 ,  H01L27/2472 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/861 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.

Abstract translation: 提供了包括设置在埋地导线上的多个访问装置的半导体阵列及其形成方法。 接入装置各自包括具有由相反掺杂剂类型的沟道区域隔开的源极区域和漏极区域以及与该晶体管相关联的存取管线的晶体管。 接入线路可以与一个或多个晶体管电耦合，并且可以可操作地耦合到电压源。 访问设备可以以一个或多个导线上的阵列形成。 可以通过将半导体器件与诸如互补金属氧化物半导体（CMOS）器件的一个或多个存储器半导体阵列或常规逻辑器件集成来形成系统。

公开(公告)号：US20130134503A1

公开(公告)日：2013-05-30

申请号：US13751902

申请日：2013-01-28

Applicant: Micron Technology, Inc.

Inventor： John Zahurak ,  Sanh D. Tang ,  Gurtej S. Sandhu

IPC: H01L29/78

CPC classification number: H01L21/823487 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/105 ,  H01L27/24 ,  H01L29/66666 ,  H01L29/7827

Abstract: Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts.

Abstract translation: 形成具有支柱的存储器单元阵列和存储单元阵列的方法。 单个柱可以具有由半导体柱上的体半导体材料和牺牲帽形成的半导体柱。 源区可以在柱的列之间，并且栅极线沿着柱柱延伸并且与相应的源极区域间隔开。 每个栅极线沿着一列柱围绕半导体柱的一部分。 可以选择性地去除牺牲帽结构，从而形成露出相应半导体柱的顶部的自对准开口。 形成在自对准开口中的单独的漏极触点电连接到相应的半导体柱。